_primary.vhd

来自「SPI 总线协议源码SPI 总线协议源码SPI 总线协议源码」· VHDL 代码 · 共 26 行

library verilog;
use verilog.vl_types.all;
entity spi_top is
    generic(
        tp              : integer := 1
    );
    port(
        wb_clk_i        : in     vl_logic;
        wb_rst_i        : in     vl_logic;
        wb_adr_i        : in     vl_logic_vector(4 downto 0);
        wb_dat_i        : in     vl_logic_vector(31 downto 0);
        wb_dat_o        : out    vl_logic_vector(31 downto 0);
        wb_sel_i        : in     vl_logic_vector(3 downto 0);
        wb_we_i         : in     vl_logic;
        wb_stb_i        : in     vl_logic;
        wb_cyc_i        : in     vl_logic;
        wb_ack_o        : out    vl_logic;
        wb_err_o        : out    vl_logic;
        wb_int_o        : out    vl_logic;
        ss_pad_o        : out    vl_logic_vector(7 downto 0);
        sclk_pad_o      : out    vl_logic;
        mosi_pad_o      : out    vl_logic;
        miso_pad_i      : in     vl_logic
    );
end spi_top;