edma3_dm648_cfg.c

来自「vicp做为dm6446上的硬件加速器」· C语言 代码 · 共 610 行 · 第 1/2 页

        4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, 7u,
        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 18u, 19u,
        20u, 21u, 22u, 23u,
        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
        32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
        40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
        48u, 49u, 50u, 51u,
        52u, 53u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
        EDMA3_RM_CH_NO_TCC_MAP, 63u
/**
 * These channel mappings make 12 DMA channels FREE to be alloacted
 * by the Driver for ANY DMA channel type of requests.
 * To allocate 2 more ANY DMA channels (i.e. a total of 14), comment out
 * the above code and uncomment the following code.
 * It will take 2 I2C DMA channels also.

        0u, 1u, 2u, 3u,
        4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, 7u,
        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 18u, 19u,
        20u, 21u, 22u, 23u,
        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
        32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
        40u, 41u, 42u, 43u,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 46u, 47u,
        48u, 49u, 50u, 51u,
        52u, 53u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
        EDMA3_RM_CH_NO_TCC_MAP, 63u
 */
        },

    /**
     * \brief Mapping of DMA channels to Hardware Events from
     * various peripherals, which use EDMA for data transfer.
     * All channels need not be mapped, some can be free also.
     */
        {
        DMA_CHANNEL_TO_EVENT_MAPPING_0,
        DMA_CHANNEL_TO_EVENT_MAPPING_1
        }
    }
};


/* Default RM Instance Initialization Configuration */
EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_REGION] =
{
        {
          {
            /* Resources owned by Region 0 */
            /* ownPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* ownDmaChannels */
            {0x0u, 0x0u},

            /* ownQdmaChannels */
            {0x0u},

            /* ownTccs */
            {0x0u, 0x0u},

            /* Resources reserved by Region 0 */
            /* resvdPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* resvdDmaChannels */
            {0x0u, 0x0u},

            /* resvdQdmaChannels */
            {0x0u},

            /* resvdTccs */
            {0x0u, 0x0u},
          },

          {
            /* Resources owned by Region 1 */
            /* ownPaRAMSets */
            {0xFFFFFFC0u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
            0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
            0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u},

            /* ownDmaChannels */
            {0xFFFFFFC0u, 0xFFFFFFFFu},

            /* ownQdmaChannels */
            {0x00000080u},

            /* ownTccs */
            {0xFFFFFFC0u, 0xFFFFFFFFu},

            /* Resources reserved by Region 1 */
            /* resvdPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u},

            /* resvdDmaChannels */
            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},

            /* resvdQdmaChannels */
            {0x0u},

            /* resvdTccs */
            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
          },

          {
            /* Resources owned by Region 2 */
            /* ownPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* ownDmaChannels */
            {0x0u, 0x0u},

            /* ownQdmaChannels */
            {0x0u},

            /* ownTccs */
            {0x0u, 0x0u},

            /* Resources reserved by Region 2 */
            /* resvdPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* resvdDmaChannels */
            {0x0u, 0x0u},

            /* resvdQdmaChannels */
            {0x0u},

            /* resvdTccs */
            {0x0u, 0x0u},
          },

          {
            /* Resources owned by Region 3 */
            /* ownPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* ownDmaChannels */
            {0x0u, 0x0u},

            /* ownQdmaChannels */
            {0x0u},

            /* ownTccs */
            {0x0u, 0x0u},

            /* Resources reserved by Region 3 */
            /* resvdPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* resvdDmaChannels */
            {0x0u, 0x0u},

            /* resvdQdmaChannels */
            {0x0u},

            /* resvdTccs */
            {0x0u, 0x0u},
          },

          {
            /* Resources owned by Region 4 */
            /* ownPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* ownDmaChannels */
            {0x0u, 0x0u},

            /* ownQdmaChannels */
            {0x0u},

            /* ownTccs */
            {0x0u, 0x0u},

            /* Resources reserved by Region 4 */
            /* resvdPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* resvdDmaChannels */
            {0x0u, 0x0u},

            /* resvdQdmaChannels */
            {0x0u},

            /* resvdTccs */
            {0x0u, 0x0u},
          },

          {
            /* Resources owned by Region 5 */
            /* ownPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* ownDmaChannels */
            {0x0u, 0x0u},

            /* ownQdmaChannels */
            {0x0u},

            /* ownTccs */
            {0x0u, 0x0u},

            /* Resources reserved by Region 5 */
            /* resvdPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* resvdDmaChannels */
            {0x0u, 0x0u},

            /* resvdQdmaChannels */
            {0x0u},

            /* resvdTccs */
            {0x0u, 0x0u},
          },

          {
            /* Resources owned by Region 6 */
            /* ownPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* ownDmaChannels */
            {0x0u, 0x0u},

            /* ownQdmaChannels */
            {0x0u},

            /* ownTccs */
            {0x0u, 0x0u},

            /* Resources reserved by Region 6 */
            /* resvdPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* resvdDmaChannels */
            {0x0u, 0x0u},

            /* resvdQdmaChannels */
            {0x0u},

            /* resvdTccs */
            {0x0u, 0x0u},
          },

          {
            /* Resources owned by Region 7 */
            /* ownPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* ownDmaChannels */
            {0x0u, 0x0u},

            /* ownQdmaChannels */
            {0x0u},

            /* ownTccs */
            {0x0u, 0x0u},

            /* Resources reserved by Region 7 */
            /* resvdPaRAMSets */
            {0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u,
            0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u, 0x0u},

            /* resvdDmaChannels */
            {0x0u, 0x0u},

            /* resvdQdmaChannels */
            {0x0u},

            /* resvdTccs */
            {0x0u, 0x0u},
          }
        }
};

/* End of File */