📄 edma3resmgr.c
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/** \file edma3resmgr.c
\brief EDMA3 Controller Resource Manager Interface Implementation
This file contains Resource Manager Implementation for the EDMA3 Controller.
(C) Copyright 2006, Texas Instruments, Inc
\version 0.0.1 Purushotam Kumar - Created
0.1.0 Joseph Fernandez - Made generic
- Added documentation
- Moved SoC specific defines
to SoC specific header.
0.2.0 Anuj Aggarwal - Modified it for EDMA3 package
- Added multiple instances
capability
0.2.1 Anuj Aggarwal - Modified it for more run time
configuration.
- Made EDMA3 package OS
independent.
0.2.2 Anuj Aggarwal - Critical section handling code
modification. Uses semaphore and
interrupts disabling mechanism
for resource sharing.
0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
- IPR bit clearing in RM ISR
issue fixed.
- Sample application made generic
0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC
mapping, to fix QDMA missed
event issue.
0.3.2 Anuj Aggarwal - Added support for POLL mode
- Added a new API to modify the
CC Register.
1.0.0 Anuj Aggarwal - Fixed resource allocation related
bugs.
1.0.0.1 Anuj Aggarwal - Fixed spurious missed event
generation related bug.
1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC
compliant.
1.0.0.3 Anuj Aggarwal - Changed the directory structure
as per RTSC standard.
1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate
logical channels
b) Created EDMA3 config files
for different platforms
c) Misc changes
1.02.00.01 Anuj Aggarwal - a) Added DM6467 support
b) Fixed some MRs
1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files
b) IOCTL Interface added.
c) Fixed some MRs.
1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs.
b) Number of maximum Resource
Manager Instances is configurable.
c) Header files modified to have
extern "C" declarations.
*/
/* Resource Manager Internal Header Files */
#include <ti/sdo/edma3/rm/src/edma3resmgr.h>
/* Instrumentation Header File */
#ifdef EDMA3_INSTRUMENTATION_ENABLED
#include <ti/sdo/edma3/rm/src/edma3_log.h>
#endif
/* Global Defines, need to re-compile if values are changed */
/*---------------------------------------------------------------------------*/
/**
* \brief EDMA3 Resource Manager behaviour of clearing CC ERROR interrupts.
* This macro controls the driver to enable/disable clearing of error
* status of all channels.
*
* On disabling this (with value 0x0), the channels owned by the region
* is cleared and its expected that some other entity is responsible for
* clearing the error status for channels not owned.
*
* Its recomended that this flag is a positive value, to ensure that
* error flags are cleared for all the channels.
*/
#define EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS (TRUE)
/**
* \brief EDMA3 Resource Manager retry count to check the pending interrupts inside ISR.
* This macro controls the driver to check the pending interrupt for
* 'n' number of times.
* Minumum value is 1.
*/
#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT (10u)
/**
* \brief EDMA3 Resource Manager retry count to check the pending CC Error Interrupt inside ISR
* This macro controls the driver to check the pending CC Error
* interrupt for 'n' number of times.
* Minumum value is 1.
*/
#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT (10u)
/* Externel Variables */
/*---------------------------------------------------------------------------*/
/**
* Maximum Resource Manager Instances supported by the EDMA3 Package.
*/
extern const unsigned int EDMA3_MAX_RM_INSTANCES;
/**
* \brief Static Configuration structure for EDMA3
* controller, to provide Global SoC specific Information.
*
* This configuration info can also be provided by the user at run-time,
* while calling EDMA3_RM_create (). If not provided at run-time,
* this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
* for the specified platform.
*/
extern EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES];
/**
* \brief Default Static Region Specific Configuration structure for
* EDMA3 controller, to provide region specific Information.
*/
extern EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
/**
* \brief Region Specific Configuration structure for
* EDMA3 controller, to provide region specific Information.
*
* This configuration info can also be provided by the user at run-time,
* while calling EDMA3_RM_open (). If not provided at run-time,
* this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
* for the specified platform.
*/
extern EDMA3_RM_InstanceInitConfig *userInitConfig;
extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
/**
* Handles of EDMA3 Resource Manager Instances.
*
* Used to maintain information of the EDMA3 RM Instances
* for each HW controller.
* There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per
* EDMA3 HW.
*/
extern EDMA3_RM_Instance *resMgrInstance;
extern EDMA3_RM_Instance *ptrRMIArray;
/* Globals */
/*---------------------------------------------------------------------------*/
/**
* \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
*
* Typically one RM object will cater to one EDMA3 HW controller
* and will have all the global config information.
*/
EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
/**
* Global Array to store the mapping between DMA channels and Interrupt
* channels i.e. TCCs.
* DMA channel X can use any TCC Y. Transfer completion
* interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error
* interrupt will occur on DMA channel X (EMR/EMRH register, bit X). In that
* scenario, this DMA channel <-> TCC mapping will be used to point to
* the correct callback function.
*/
static unsigned int edma3DmaChTccMapping [EDMA3_MAX_DMA_CH];
/**
* Global Array to store the mapping between QDMA channels and Interrupt
* channels i.e. TCCs.
* QDMA channel X can use any TCC Y. Transfer completion
* interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error
* interrupt will occur on QDMA channel X (QEMR register, bit X). In that
* scenario, this QDMA channel <-> TCC mapping will be used to point to
* the correct callback function.
*/
static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_QDMA_CH];
/**
* Global Array to maintain the Callback details registered
* against a particular TCC. Used to call the callback
* functions linked to the particular channel.
*/
static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_TCC];
/** edma3RegionId will be updated ONCE using the parameter regionId passed to
* the EDMA3_RM_open() function, for the Master RM instance (one who
* configures the Global Registers).
* This global variable will be used within the Interrupt handlers to know
* which shadow region registers to access. All other interrupts coming
* from other shadow regions will not be handled.
*/
static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS;
/** masterExists will be updated when the Master RM Instance modifies the
* Global EDMA3 configuration registers. It is used to prevent any other
* Master RM Instance creation.
*/
static unsigned short masterExists = FALSE;
/**
* Number of PaRAM Sets actually present on the SoC. This will be updated
* while creating the Resource Manager Object.
*/
unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
/**
* The list of Interrupt Channels which get allocated while requesting the
* TCC. It will be used while checking the IPR/IPRH bits in the RM ISR.
*/
static unsigned int allocatedTCCs[2u] = {0x0u, 0x0u};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
static unsigned int contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
static unsigned int contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
static unsigned int contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
static unsigned int contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];
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