edma3_rl_tc.h

来自「vicp做为dm6446上的硬件加速器」· C头文件 代码 · 共 807 行 · 第 1/2 页

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#define EDMA3_TCRL_ERRCMD_SET_RESETVAL   (0x00000000u)

/*----SET Tokens----*/
#define EDMA3_TCRL_ERRCMD_SET_SET        (0x00000001u)

#define EDMA3_TCRL_ERRCMD_EVAL_MASK      (0x00000001u)
#define EDMA3_TCRL_ERRCMD_EVAL_SHIFT     (0x00000000u)
#define EDMA3_TCRL_ERRCMD_EVAL_RESETVAL  (0x00000000u)

/*----EVAL Tokens----*/
#define EDMA3_TCRL_ERRCMD_EVAL_EVAL      (0x00000001u)

#define EDMA3_TCRL_ERRCMD_RESETVAL       (0x00000000u)

/* RDRATE */

#define EDMA3_TCRL_RDRATE_RDRATE_MASK    (0x00000007u)
#define EDMA3_TCRL_RDRATE_RDRATE_SHIFT   (0x00000000u)
#define EDMA3_TCRL_RDRATE_RDRATE_RESETVAL (0x00000000u)

/*----RDRATE Tokens----*/
#define EDMA3_TCRL_RDRATE_RDRATE_AFAP    (0x00000000u)
#define EDMA3_TCRL_RDRATE_RDRATE_4CYCLE  (0x00000001u)
#define EDMA3_TCRL_RDRATE_RDRATE_8CYCLE  (0x00000002u)
#define EDMA3_TCRL_RDRATE_RDRATE_16CYCLE (0x00000003u)
#define EDMA3_TCRL_RDRATE_RDRATE_32CYCLE (0x00000004u)

#define EDMA3_TCRL_RDRATE_RESETVAL       (0x00000000u)

/* POPT */

#define EDMA3_TCRL_POPT_TCCHEN_MASK      (0x00400000u)
#define EDMA3_TCRL_POPT_TCCHEN_SHIFT     (0x00000016u)
#define EDMA3_TCRL_POPT_TCCHEN_RESETVAL  (0x00000000u)

/*----TCCHEN Tokens----*/
#define EDMA3_TCRL_POPT_TCCHEN_DISABLE   (0x00000000u)
#define EDMA3_TCRL_POPT_TCCHEN_ENABLE    (0x00000001u)

#define EDMA3_TCRL_POPT_TCINTEN_MASK     (0x00100000u)
#define EDMA3_TCRL_POPT_TCINTEN_SHIFT    (0x00000014u)
#define EDMA3_TCRL_POPT_TCINTEN_RESETVAL (0x00000000u)

/*----TCINTEN Tokens----*/
#define EDMA3_TCRL_POPT_TCINTEN_DISABLE  (0x00000000u)
#define EDMA3_TCRL_POPT_TCINTEN_ENABLE   (0x00000001u)

#define EDMA3_TCRL_POPT_TCC_MASK         (0x0003F000u)
#define EDMA3_TCRL_POPT_TCC_SHIFT        (0x0000000Cu)
#define EDMA3_TCRL_POPT_TCC_RESETVAL     (0x00000000u)

#define EDMA3_TCRL_POPT_FWID_MASK        (0x00000700u)
#define EDMA3_TCRL_POPT_FWID_SHIFT       (0x00000008u)
#define EDMA3_TCRL_POPT_FWID_RESETVAL    (0x00000000u)

/*----FWID Tokens----*/
#define EDMA3_TCRL_POPT_FWID_8BIT        (0x00000000u)
#define EDMA3_TCRL_POPT_FWID_16BIT       (0x00000001u)
#define EDMA3_TCRL_POPT_FWID_32BIT       (0x00000002u)
#define EDMA3_TCRL_POPT_FWID_64BIT       (0x00000003u)
#define EDMA3_TCRL_POPT_FWID_128BIT      (0x00000004u)
#define EDMA3_TCRL_POPT_FWID_256BIT      (0x00000005u)

#define EDMA3_TCRL_POPT_PRI_MASK         (0x00000070u)
#define EDMA3_TCRL_POPT_PRI_SHIFT        (0x00000004u)
#define EDMA3_TCRL_POPT_PRI_RESETVAL     (0x00000000u)

#define EDMA3_TCRL_POPT_DAM_MASK         (0x00000002u)
#define EDMA3_TCRL_POPT_DAM_SHIFT        (0x00000001u)
#define EDMA3_TCRL_POPT_DAM_RESETVAL     (0x00000000u)

/*----DAM Tokens----*/
#define EDMA3_TCRL_POPT_DAM_INCR         (0x00000000u)
#define EDMA3_TCRL_POPT_DAM_FIFO         (0x00000001u)

#define EDMA3_TCRL_POPT_SAM_MASK         (0x00000001u)
#define EDMA3_TCRL_POPT_SAM_SHIFT        (0x00000000u)
#define EDMA3_TCRL_POPT_SAM_RESETVAL     (0x00000000u)

/*----SAM Tokens----*/
#define EDMA3_TCRL_POPT_SAM_INCR         (0x00000000u)
#define EDMA3_TCRL_POPT_SAM_FIFO         (0x00000001u)

#define EDMA3_TCRL_POPT_RESETVAL         (0x00000000u)

/* PSRC */

#define EDMA3_TCRL_PSRC_SADDR_MASK       (0xFFFFFFFFu)
#define EDMA3_TCRL_PSRC_SADDR_SHIFT      (0x00000000u)
#define EDMA3_TCRL_PSRC_SADDR_RESETVAL   (0x00000000u)

#define EDMA3_TCRL_PSRC_RESETVAL         (0x00000000u)

/* PCNT */

#define EDMA3_TCRL_PCNT_BCNT_MASK        (0xFFFF0000u)
#define EDMA3_TCRL_PCNT_BCNT_SHIFT       (0x00000010u)
#define EDMA3_TCRL_PCNT_BCNT_RESETVAL    (0x00000000u)

#define EDMA3_TCRL_PCNT_ACNT_MASK        (0x0000FFFFu)
#define EDMA3_TCRL_PCNT_ACNT_SHIFT       (0x00000000u)
#define EDMA3_TCRL_PCNT_ACNT_RESETVAL    (0x00000000u)

#define EDMA3_TCRL_PCNT_RESETVAL         (0x00000000u)

/* PDST */

#define EDMA3_TCRL_PDST_DADDR_MASK       (0xFFFFFFFFu)
#define EDMA3_TCRL_PDST_DADDR_SHIFT      (0x00000000u)
#define EDMA3_TCRL_PDST_DADDR_RESETVAL   (0x00000000u)

#define EDMA3_TCRL_PDST_RESETVAL         (0x00000000u)

/* PBIDX */

#define EDMA3_TCRL_PBIDX_DBIDX_MASK      (0xFFFF0000u)
#define EDMA3_TCRL_PBIDX_DBIDX_SHIFT     (0x00000010u)
#define EDMA3_TCRL_PBIDX_DBIDX_RESETVAL  (0x00000000u)

#define EDMA3_TCRL_PBIDX_SBIDX_MASK      (0x0000FFFFu)
#define EDMA3_TCRL_PBIDX_SBIDX_SHIFT     (0x00000000u)
#define EDMA3_TCRL_PBIDX_SBIDX_RESETVAL  (0x00000000u)

#define EDMA3_TCRL_PBIDX_RESETVAL        (0x00000000u)

/* PMPPRXY */

#define EDMA3_TCRL_PMPPRXY_PRIV_MASK     (0x00000100u)
#define EDMA3_TCRL_PMPPRXY_PRIV_SHIFT    (0x00000008u)
#define EDMA3_TCRL_PMPPRXY_PRIV_RESETVAL (0x00000000u)

/*----PRIV Tokens----*/
#define EDMA3_TCRL_PMPPRXY_PRIV_USER     (0x00000000u)
#define EDMA3_TCRL_PMPPRXY_PRIV_SUPERVISOR (0x00000001u)

#define EDMA3_TCRL_PMPPRXY_PRIVID_MASK   (0x0000000Fu)
#define EDMA3_TCRL_PMPPRXY_PRIVID_SHIFT  (0x00000000u)
#define EDMA3_TCRL_PMPPRXY_PRIVID_RESETVAL (0x00000000u)

#define EDMA3_TCRL_PMPPRXY_RESETVAL      (0x00000000u)

/* SAOPT */

#define EDMA3_TCRL_SAOPT_TCCHEN_MASK     (0x00400000u)
#define EDMA3_TCRL_SAOPT_TCCHEN_SHIFT    (0x00000016u)
#define EDMA3_TCRL_SAOPT_TCCHEN_RESETVAL (0x00000000u)

/*----TCCHEN Tokens----*/
#define EDMA3_TCRL_SAOPT_TCCHEN_DISABLE  (0x00000000u)
#define EDMA3_TCRL_SAOPT_TCCHEN_ENABLE   (0x00000001u)

#define EDMA3_TCRL_SAOPT_TCINTEN_MASK    (0x00100000u)
#define EDMA3_TCRL_SAOPT_TCINTEN_SHIFT   (0x00000014u)
#define EDMA3_TCRL_SAOPT_TCINTEN_RESETVAL (0x00000000u)

/*----TCINTEN Tokens----*/
#define EDMA3_TCRL_SAOPT_TCINTEN_DISABLE (0x00000000u)
#define EDMA3_TCRL_SAOPT_TCINTEN_ENABLE  (0x00000001u)

#define EDMA3_TCRL_SAOPT_TCC_MASK        (0x0003F000u)
#define EDMA3_TCRL_SAOPT_TCC_SHIFT       (0x0000000Cu)
#define EDMA3_TCRL_SAOPT_TCC_RESETVAL    (0x00000000u)

#define EDMA3_TCRL_SAOPT_FWID_MASK       (0x00000700u)
#define EDMA3_TCRL_SAOPT_FWID_SHIFT      (0x00000008u)
#define EDMA3_TCRL_SAOPT_FWID_RESETVAL   (0x00000000u)

/*----FWID Tokens----*/
#define EDMA3_TCRL_SAOPT_FWID_8BIT       (0x00000000u)
#define EDMA3_TCRL_SAOPT_FWID_16BIT      (0x00000001u)
#define EDMA3_TCRL_SAOPT_FWID_32BIT      (0x00000002u)
#define EDMA3_TCRL_SAOPT_FWID_64BIT      (0x00000003u)
#define EDMA3_TCRL_SAOPT_FWID_128BIT     (0x00000004u)
#define EDMA3_TCRL_SAOPT_FWID_256BIT     (0x00000005u)

#define EDMA3_TCRL_SAOPT_PRI_MASK        (0x00000070u)
#define EDMA3_TCRL_SAOPT_PRI_SHIFT       (0x00000004u)
#define EDMA3_TCRL_SAOPT_PRI_RESETVAL    (0x00000000u)

#define EDMA3_TCRL_SAOPT_DAM_MASK        (0x00000002u)
#define EDMA3_TCRL_SAOPT_DAM_SHIFT       (0x00000001u)
#define EDMA3_TCRL_SAOPT_DAM_RESETVAL    (0x00000000u)

/*----DAM Tokens----*/
#define EDMA3_TCRL_SAOPT_DAM_INCR        (0x00000000u)
#define EDMA3_TCRL_SAOPT_DAM_FIFO        (0x00000001u)

#define EDMA3_TCRL_SAOPT_SAM_MASK        (0x00000001u)
#define EDMA3_TCRL_SAOPT_SAM_SHIFT       (0x00000000u)
#define EDMA3_TCRL_SAOPT_SAM_RESETVAL    (0x00000000u)

/*----SAM Tokens----*/
#define EDMA3_TCRL_SAOPT_SAM_INCR        (0x00000000u)
#define EDMA3_TCRL_SAOPT_SAM_FIFO        (0x00000001u)

#define EDMA3_TCRL_SAOPT_RESETVAL        (0x00000000u)

/* SASRC */

#define EDMA3_TCRL_SASRC_SADDR_MASK      (0xFFFFFFFFu)
#define EDMA3_TCRL_SASRC_SADDR_SHIFT     (0x00000000u)
#define EDMA3_TCRL_SASRC_SADDR_RESETVAL  (0x00000000u)

#define EDMA3_TCRL_SASRC_RESETVAL        (0x00000000u)

/* SACNT */

#define EDMA3_TCRL_SACNT_BCNT_MASK       (0xFFFF0000u)
#define EDMA3_TCRL_SACNT_BCNT_SHIFT      (0x00000010u)
#define EDMA3_TCRL_SACNT_BCNT_RESETVAL   (0x00000000u)

#define EDMA3_TCRL_SACNT_ACNT_MASK       (0x0000FFFFu)
#define EDMA3_TCRL_SACNT_ACNT_SHIFT      (0x00000000u)
#define EDMA3_TCRL_SACNT_ACNT_RESETVAL   (0x00000000u)

#define EDMA3_TCRL_SACNT_RESETVAL        (0x00000000u)

/* SADST */

#define EDMA3_TCRL_SADST_RESETVAL        (0x00000000u)

/* SABIDX */

#define EDMA3_TCRL_SABIDX_DBIDX_MASK     (0xFFFF0000u)
#define EDMA3_TCRL_SABIDX_DBIDX_SHIFT    (0x00000010u)
#define EDMA3_TCRL_SABIDX_DBIDX_RESETVAL (0x00000000u)

#define EDMA3_TCRL_SABIDX_SBIDX_MASK     (0x0000FFFFu)
#define EDMA3_TCRL_SABIDX_SBIDX_SHIFT    (0x00000000u)
#define EDMA3_TCRL_SABIDX_SBIDX_RESETVAL (0x00000000u)

#define EDMA3_TCRL_SABIDX_RESETVAL       (0x00000000u)

/* SAMPPRXY */

#define EDMA3_TCRL_SAMPPRXY_PRIV_MASK    (0x00000100u)
#define EDMA3_TCRL_SAMPPRXY_PRIV_SHIFT   (0x00000008u)
#define EDMA3_TCRL_SAMPPRXY_PRIV_RESETVAL (0x00000000u)

/*----PRIV Tokens----*/
#define EDMA3_TCRL_SAMPPRXY_PRIV_USER    (0x00000000u)
#define EDMA3_TCRL_SAMPPRXY_PRIV_SUPERVISOR (0x00000001u)

#define EDMA3_TCRL_SAMPPRXY_PRIVID_MASK  (0x0000000Fu)
#define EDMA3_TCRL_SAMPPRXY_PRIVID_SHIFT (0x00000000u)
#define EDMA3_TCRL_SAMPPRXY_PRIVID_RESETVAL (0x00000000u)

#define EDMA3_TCRL_SAMPPRXY_RESETVAL     (0x00000000u)

/* SACNTRLD */

#define EDMA3_TCRL_SACNTRLD_ACNTRLD_MASK (0x0000FFFFu)
#define EDMA3_TCRL_SACNTRLD_ACNTRLD_SHIFT (0x00000000u)
#define EDMA3_TCRL_SACNTRLD_ACNTRLD_RESETVAL (0x00000000u)

#define EDMA3_TCRL_SACNTRLD_RESETVAL     (0x00000000u)

/* SASRCBREF */

#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_MASK (0xFFFFFFFFu)
#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_SHIFT (0x00000000u)
#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_RESETVAL (0x00000000u)

#define EDMA3_TCRL_SASRCBREF_RESETVAL    (0x00000000u)

/* SADSTBREF */

#define EDMA3_TCRL_SADSTBREF_RESETVAL    (0x00000000u)

/* DFCNTRLD */

#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_MASK (0x0000FFFFu)
#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_SHIFT (0x00000000u)
#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_RESETVAL (0x00000000u)

#define EDMA3_TCRL_DFCNTRLD_RESETVAL     (0x00000000u)

/* DFSRCBREF */

#define EDMA3_TCRL_DFSRCBREF_RESETVAL    (0x00000000u)

/* DFDSTBREF */

#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_MASK (0xFFFFFFFFu)
#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_SHIFT (0x00000000u)
#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_RESETVAL (0x00000000u)

#define EDMA3_TCRL_DFDSTBREF_RESETVAL    (0x00000000u)

/* DFOPT */

#define EDMA3_TCRL_DFOPT_TCCHEN_MASK     (0x00400000u)
#define EDMA3_TCRL_DFOPT_TCCHEN_SHIFT    (0x00000016u)
#define EDMA3_TCRL_DFOPT_TCCHEN_RESETVAL (0x00000000u)

/*----TCCHEN Tokens----*/
#define EDMA3_TCRL_DFOPT_TCCHEN_DISABLE  (0x00000000u)
#define EDMA3_TCRL_DFOPT_TCCHEN_ENABLE   (0x00000001u)

#define EDMA3_TCRL_DFOPT_TCINTEN_MASK    (0x00100000u)
#define EDMA3_TCRL_DFOPT_TCINTEN_SHIFT   (0x00000014u)
#define EDMA3_TCRL_DFOPT_TCINTEN_RESETVAL (0x00000000u)

/*----TCINTEN Tokens----*/
#define EDMA3_TCRL_DFOPT_TCINTEN_DISABLE (0x00000000u)
#define EDMA3_TCRL_DFOPT_TCINTEN_ENABLE  (0x00000001u)

#define EDMA3_TCRL_DFOPT_TCC_MASK        (0x0003F000u)
#define EDMA3_TCRL_DFOPT_TCC_SHIFT       (0x0000000Cu)
#define EDMA3_TCRL_DFOPT_TCC_RESETVAL    (0x00000000u)

#define EDMA3_TCRL_DFOPT_FWID_MASK       (0x00000700u)
#define EDMA3_TCRL_DFOPT_FWID_SHIFT      (0x00000008u)
#define EDMA3_TCRL_DFOPT_FWID_RESETVAL   (0x00000000u)

/*----FWID Tokens----*/
#define EDMA3_TCRL_DFOPT_FWID_8BIT       (0x00000000u)
#define EDMA3_TCRL_DFOPT_FWID_16BIT      (0x00000001u)
#define EDMA3_TCRL_DFOPT_FWID_32BIT      (0x00000002u)
#define EDMA3_TCRL_DFOPT_FWID_64BIT      (0x00000003u)
#define EDMA3_TCRL_DFOPT_FWID_128BIT     (0x00000004u)
#define EDMA3_TCRL_DFOPT_FWID_256BIT     (0x00000005u)

#define EDMA3_TCRL_DFOPT_PRI_MASK        (0x00000070u)
#define EDMA3_TCRL_DFOPT_PRI_SHIFT       (0x00000004u)
#define EDMA3_TCRL_DFOPT_PRI_RESETVAL    (0x00000000u)

#define EDMA3_TCRL_DFOPT_DAM_MASK        (0x00000002u)
#define EDMA3_TCRL_DFOPT_DAM_SHIFT       (0x00000001u)
#define EDMA3_TCRL_DFOPT_DAM_RESETVAL    (0x00000000u)

/*----DAM Tokens----*/
#define EDMA3_TCRL_DFOPT_DAM_INCR        (0x00000000u)
#define EDMA3_TCRL_DFOPT_DAM_FIFO        (0x00000001u)

#define EDMA3_TCRL_DFOPT_SAM_MASK        (0x00000001u)
#define EDMA3_TCRL_DFOPT_SAM_SHIFT       (0x00000000u)
#define EDMA3_TCRL_DFOPT_SAM_RESETVAL    (0x00000000u)

/*----SAM Tokens----*/
#define EDMA3_TCRL_DFOPT_SAM_INCR        (0x00000000u)
#define EDMA3_TCRL_DFOPT_SAM_FIFO        (0x00000001u)

#define EDMA3_TCRL_DFOPT_RESETVAL        (0x00000000u)

/* DFSRC */

#define EDMA3_TCRL_DFSRC_RESETVAL        (0x00000000u)

/* DFCNT */

#define EDMA3_TCRL_DFCNT_BCNT_MASK       (0xFFFF0000u)
#define EDMA3_TCRL_DFCNT_BCNT_SHIFT      (0x00000010u)
#define EDMA3_TCRL_DFCNT_BCNT_RESETVAL   (0x00000000u)

#define EDMA3_TCRL_DFCNT_ACNT_MASK       (0x0000FFFFu)
#define EDMA3_TCRL_DFCNT_ACNT_SHIFT      (0x00000000u)
#define EDMA3_TCRL_DFCNT_ACNT_RESETVAL   (0x00000000u)

#define EDMA3_TCRL_DFCNT_RESETVAL        (0x00000000u)

/* DFDST */

#define EDMA3_TCRL_DFDST_DADDR_MASK      (0xFFFFFFFFu)
#define EDMA3_TCRL_DFDST_DADDR_SHIFT     (0x00000000u)
#define EDMA3_TCRL_DFDST_DADDR_RESETVAL  (0x00000000u)

#define EDMA3_TCRL_DFDST_RESETVAL        (0x00000000u)

/* DFBIDX */

#define EDMA3_TCRL_DFBIDX_DBIDX_MASK     (0xFFFF0000u)
#define EDMA3_TCRL_DFBIDX_DBIDX_SHIFT    (0x00000010u)
#define EDMA3_TCRL_DFBIDX_DBIDX_RESETVAL (0x00000000u)

#define EDMA3_TCRL_DFBIDX_SBIDX_MASK     (0x0000FFFFu)
#define EDMA3_TCRL_DFBIDX_SBIDX_SHIFT    (0x00000000u)
#define EDMA3_TCRL_DFBIDX_SBIDX_RESETVAL (0x00000000u)

#define EDMA3_TCRL_DFBIDX_RESETVAL       (0x00000000u)

/* DFMPPRXY */

#define EDMA3_TCRL_DFMPPRXY_PRIV_MASK    (0x00000100u)
#define EDMA3_TCRL_DFMPPRXY_PRIV_SHIFT   (0x00000008u)
#define EDMA3_TCRL_DFMPPRXY_PRIV_RESETVAL (0x00000000u)

/*----PRIV Tokens----*/
#define EDMA3_TCRL_DFMPPRXY_PRIV_USER    (0x00000000u)
#define EDMA3_TCRL_DFMPPRXY_PRIV_SUPERVISOR (0x00000001u)

#define EDMA3_TCRL_DFMPPRXY_PRIVID_MASK  (0x0000000Fu)
#define EDMA3_TCRL_DFMPPRXY_PRIVID_SHIFT (0x00000000u)
#define EDMA3_TCRL_DFMPPRXY_PRIVID_RESETVAL (0x00000000u)

#define EDMA3_TCRL_DFMPPRXY_RESETVAL     (0x00000000u)

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif  /* _EDMA3_RL_TC_H_ */
12

edma3_rl_tc.h - 源码说明

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