edma3_drx40x_cfg.c

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/******************************************************************************
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**|         Copyright (c) 1998-2006 Texas Instruments Incorporated          |**
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******************************************************************************/

/** \file   edma3_dm648_cfg.c
 *  \brief  EDMA3 Driver Adaptation Configuration File (Soc Specific) for DM648
 *          platform.
 *
 *  This file contains configuration data for adaptation of EDMA3 RM
 *
 *  (C) Copyright 2006, Texas Instruments, Inc
 *
 *  \version    0.1     Anuj Aggarwal     - Created
 */

#include <ti/sdo/edma3/rm/edma3_rm.h>

/** Total number of DMA Channels supported by the EDMA3 Controller */
#define NUM_DMA_CHANNELS                        (64u)
/** Total number of QDMA Channels supported by the EDMA3 Controller */
#define NUM_QDMA_CHANNELS                       (8u)
/** Total number of TCCs supported by the EDMA3 Controller */
#define NUM_TCC                                 (64u)
/** Total number of PaRAM Sets supported by the EDMA3 Controller */
#define NUM_PARAM_SETS                          (512u)
/** Total number of Event Queues in the EDMA3 Controller */
#define NUM_EVENT_QUEUE                         (2u)
/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
#define NUM_TC                                  (2u)
/** Number of Regions on this EDMA3 controller */
#define NUM_REGION                              (2u)

/**
 * \brief Channel mapping existence
 * A value of 0 (No channel mapping) implies that there is fixed association
 * for a channel number to a parameter entry number or, in other words,
 * PaRAM entry n corresponds to channel n.
 */
#define CHANNEL_MAPPING_EXISTENCE               (0u)
/** Existence of memory protection feature */
#define MEM_PROTECTION_EXISTENCE                (0u)

/** Global Register Region of CC Registers */
#define CC_BASE_ADDRESS                         (0x01C00000u)
/** Transfer Controller 0 Registers */
#define TC0_BASE_ADDRESS                        (0x01C10000u)
/** Transfer Controller 1 Registers */
#define TC1_BASE_ADDRESS                        (0x01C10400u)
/** Transfer Controller 2 Registers */
#define TC2_BASE_ADDRESS                        NULL
/** Transfer Controller 3 Registers */
#define TC3_BASE_ADDRESS                        NULL
/** Transfer Controller 4 Registers */
#define TC4_BASE_ADDRESS                        NULL
/** Transfer Controller 5 Registers */
#define TC5_BASE_ADDRESS                        NULL
/** Transfer Controller 6 Registers */
#define TC6_BASE_ADDRESS                        NULL
/** Transfer Controller 7 Registers */
#define TC7_BASE_ADDRESS                        NULL

#ifdef PROS_BUILD /* PROS_BUILD */
/** Interrupt no. for Transfer Completion */
#define XFER_COMPLETION_INT                     (10u)
/** Interrupt no. for CC Error */
#define CC_ERROR_INT                            (11u)
/** Interrupt no. for TC 0 Error */
#define TC0_ERROR_INT                           (12u)
/** Interrupt no. for TC 1 Error */
#define TC1_ERROR_INT                           (0u)
/** Interrupt no. for TC 2 Error */
#define TC2_ERROR_INT                           (0u)
/** Interrupt no. for TC 3 Error */
#define TC3_ERROR_INT                           (0u)
/** Interrupt no. for TC 4 Error */
#define TC4_ERROR_INT                           (0u)
/** Interrupt no. for TC 5 Error */
#define TC5_ERROR_INT                           (0u)
/** Interrupt no. for TC 6 Error */
#define TC6_ERROR_INT                           (0u)
/** Interrupt no. for TC 7 Error */
#define TC7_ERROR_INT                           (0u)

#else /* BIOS */
/** Interrupt no. for Transfer Completion */
#define XFER_COMPLETION_INT                     (42u)
/** Interrupt no. for CC Error */
#define CC_ERROR_INT                            (43u)
/** Interrupt no. for TC 0 Error */
#define TC0_ERROR_INT                           (44u)
/** Interrupt no. for TC 1 Error */
#define TC1_ERROR_INT                           (45u)
/** Interrupt no. for TC 2 Error */
#define TC2_ERROR_INT                           (0u)
/** Interrupt no. for TC 3 Error */
#define TC3_ERROR_INT                           (0u)
/** Interrupt no. for TC 4 Error */
#define TC4_ERROR_INT                           (0u)
/** Interrupt no. for TC 5 Error */
#define TC5_ERROR_INT                           (0u)
/** Interrupt no. for TC 6 Error */
#define TC6_ERROR_INT                           (0u)
/** Interrupt no. for TC 7 Error */
#define TC7_ERROR_INT                           (0u)
#endif /* PROS_BUILD*/

/**
 * \brief Mapping of DMA channels 0-31 to Hardware Events from
 * various peripherals, which use EDMA for data transfer.
 * All channels need not be mapped, some can be free also.
 * 1: Mapped
 * 0: Not mapped
 *
 * This mapping will be used to allocate DMA channels when user passes
 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 * copy). The same mapping is used to allocate the TCC when user passes
 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 *
 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 */
#define DMA_CHANNEL_TO_EVENT_MAPPING_0           0x1830FFFCu
                        /* 0001 1000 0011 0000 1111 1111 1111 1100 */
/**
 * \brief Mapping of DMA channels 32-63 to Hardware Events from
 * various peripherals, which use EDMA for data transfer.
 * All channels need not be mapped, some can be free also.
 * 1: Mapped
 * 0: Not mapped
 *
 * This mapping will be used to allocate DMA channels when user passes
 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 * copy). The same mapping is used to allocate the TCC when user passes
 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 *
 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 */
#define DMA_CHANNEL_TO_EVENT_MAPPING_1          0x19FFFE7Eu
                        /* 0001 1001 1111 1111 1111 1110 0111 1110 */

/**
 * These channel mappings make 12 DMA channels FREE to be alloacted
 * by the Driver for ANY DMA channel type of requests.
 * To allocate 2 more ANY DMA channels (i.e. a total of 14),
 * use the following define. It will take 2 I2C DMA channels.
 * #define DMA_CHANNEL_TO_EVENT_MAPPING_1          0x803FCFFFu
 */


EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
{
    {
    /** Total number of DMA Channels supported by the EDMA3 Controller */
    NUM_DMA_CHANNELS,
    /** Total number of QDMA Channels supported by the EDMA3 Controller */
    NUM_QDMA_CHANNELS,
    /** Total number of TCCs supported by the EDMA3 Controller */
    NUM_TCC,
    /** Total number of PaRAM Sets supported by the EDMA3 Controller */
    NUM_PARAM_SETS,
    /** Total number of Event Queues in the EDMA3 Controller */
    NUM_EVENT_QUEUE,
    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
    NUM_TC,
    /** Number of Regions on this EDMA3 controller */
    NUM_REGION,

    /**
     * \brief Channel mapping existence
     * A value of 0 (No channel mapping) implies that there is fixed association
     * for a channel number to a parameter entry number or, in other words,
     * PaRAM entry n corresponds to channel n.
     */
    CHANNEL_MAPPING_EXISTENCE,

    /** Existence of memory protection feature */
    MEM_PROTECTION_EXISTENCE,

    /** Global Register Region of CC Registers */
    (void *)(CC_BASE_ADDRESS),
    /** Transfer Controller (TC) Registers */
        {
        (void *)(TC0_BASE_ADDRESS),
        (void *)(TC1_BASE_ADDRESS),
        (void *)(TC2_BASE_ADDRESS),
        (void *)(TC3_BASE_ADDRESS),
        (void *)(TC4_BASE_ADDRESS),