edma3_rm.h

vicp做为dm6446上的硬件加速器

        - Use Case 20: Free the previously allocated Link channel. It will free
            the PaRAM Set used for linking.
            - result = EDMA3_RM_freeLogicalChannel (hRes, &resObj);

        - Use Case 21: Free the previously allocated logical DMA channel. It
            will also free the associated PaRAM Set and TCC.
            - resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
            - resObj.resId = dmaCh1Id;
            - result = EDMA3_RM_freeLogicalChannel (hRes, &resObj);

        - Use Case 22: Free the previously allocated logical QDMA channel. It
            will also free the associated PaRAM Set and TCC.
            - resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
            - resObj.resId = qdmaChId;
            - result = EDMA3_RM_freeLogicalChannel (hRes, &resObj);


    -# Close Resource Manager Instance
        - Steps
            - EDMA3_RM_Result    edma3Result = EDMA3_RM_SOK;

            - Unregister Interrupt Handlers first, if previously registered.
            - Delete the semaphore created during RM Instance Opening.
                - edma3Result = edma3OsSemDelete (rmSemHandle);
            - Close the EDMA3 RM Instance
                - edma3Result = EDMA3_RM_close (hRes, NULL);


    -# Delete Resource Manager Object
        - Steps
            - EDMA3_RM_Result    edma3Result = EDMA3_RM_SOK;
            - unsigned int edmaInstanceId = 0;

            - edma3Result = EDMA3_RM_delete (edmaInstanceId, NULL);

*/

/* @} Edma3RMUsage */

/*---------------------------------------------------------------------------*/
/*------------------Usage Guidelines End-------------------------------------*/
/*---------------------------------------------------------------------------*/


/**
 * \defgroup Edma3RMErrCode Error Codes
 *
 * Error Codes returned by the EDMA3 Resource Manager Layer
 *
 * @{
 */

/** Resource Manager Error Codes base define */
#define EDMA3_RM_E_BASE                             (-155)

/**
 * Resource Manager Object Not Deleted yet.
 * So the object cannot be created.
 */
#define EDMA3_RM_E_OBJ_NOT_DELETED                  (EDMA3_RM_E_BASE)

/**
 * Resource Manager Object Not Closed yet.
 * So the object cannot be deleted.
 */
#define EDMA3_RM_E_OBJ_NOT_CLOSED                  (EDMA3_RM_E_BASE-1)

/**
 * Resource Manager Object Not Opened yet
 * So the object cannot be closed.
 */
#define EDMA3_RM_E_OBJ_NOT_OPENED                  (EDMA3_RM_E_BASE-2)

/** Invalid Parameter passed to API */
#define EDMA3_RM_E_INVALID_PARAM                   (EDMA3_RM_E_BASE-3)

/** Resource requested for freeing is already free */
#define EDMA3_RM_E_RES_ALREADY_FREE                (EDMA3_RM_E_BASE-4)

/** Resource requested for allocation/freeing is not owned */
#define EDMA3_RM_E_RES_NOT_OWNED                   (EDMA3_RM_E_BASE-5)

/** Resource is not available */
#define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE     (EDMA3_RM_E_BASE-6)

/** No Resource of specified type is available */
#define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE           (EDMA3_RM_E_BASE-7)

/** Invalid State of EDMA3 RM Obj */
#define EDMA3_RM_E_INVALID_STATE                   (EDMA3_RM_E_BASE-8)

/** Maximum no of Res Mgr Instances already Opened */
#define EDMA3_RM_E_MAX_RM_INST_OPENED              (EDMA3_RM_E_BASE-9)

/**
 * More than one Res Mgr Master Instance NOT supported.
 * Only 1 master can exist.
 */
#define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS         (EDMA3_RM_E_BASE-10)

/** Callback function already registered. */
#define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED      (EDMA3_RM_E_BASE-11)

/** Semaphore related error */
#define EDMA3_RM_E_SEMAPHORE                        (EDMA3_RM_E_BASE-12)

/** Hardware feature NOT supported */
#define EDMA3_RM_E_FEATURE_UNSUPPORTED                        (EDMA3_RM_E_BASE-13)

/** EDMA3 Resource NOT allocated */
#define EDMA3_RM_E_RES_NOT_ALLOCATED                        (EDMA3_RM_E_BASE-14)

/* @} Edma3RMErrCode */




/**\typedef     EDMA3_RM_RegionId
 * \brief       EDMA3 Region Id
 *
 * Use this to assign channels/PaRAM sets/TCCs to a particular Region.
 */
typedef unsigned int EDMA3_RM_RegionId;

/**\typedef     EDMA3_RM_EventQueue
 * \brief       EDMA3 Event Queue assignment
 *
 * There can be 8 Event Queues.  Either of them can be assigned
 * to a DMA/QDMA channel using this.
 *
 */
typedef unsigned int EDMA3_RM_EventQueue;



/**\struct  EDMA3_RM_GblConfigParams
 * \brief   Init-time Configuration structure for EDMA3
 * controller, to provide Global SoC specific Information.
 *
 * This configuration structure is used to specify the EDMA3 Resource Manager
 * global settings, specific to the SoC. For e.g. number of DMA/QDMA channels,
 * number of PaRAM sets, TCCs, event queues, transfer controllers, base
 * addresses of CC global registers and TC registers, interrupt number for
 * EDMA3 transfer completion, CC error, event queues' priority, watermark
 * threshold level etc.
 * This configuration information is SoC specific and could be provided by the
 * user at run-time while creating the EDMA3 RM Object, using API
 * EDMA3_RM_create. In case user doesn't provide it, this information could be
 * taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in
 * case it is available.
 */
typedef struct  {
    /** Number of DMA Channels supported by the underlying EDMA3 Controller. */
    unsigned int        numDmaChannels;

    /** Number of QDMA Channels supported by the underlying EDMA3 Controller */
    unsigned int        numQdmaChannels;

    /**
     * Number of Interrupt Channels supported by the underlying EDMA3
     * Controller
     */
    unsigned int        numTccs;

    /** Number of PaRAM Sets supported by the underlying EDMA3 Controller */
    unsigned int        numPaRAMSets;

    /** Number of Event Queues in the underlying EDMA3 Controller */
    unsigned int        numEvtQueue;

    /**
     * Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller
     */
    unsigned int        numTcs;

    /** Number of Regions in the underlying EDMA3 Controller  */
    unsigned int        numRegions;

    /**
     * \brief Channel mapping existence
     *
     * A value of 0 (No channel mapping) implies that there is fixed
     * association between a DMA channel and a PaRAM Set or, in other words,
     * DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP
     * registers) for transfers to happen.
     *
     * A value of 1 implies the presence of DCHMAP registers for the DMA
     * channels and hence the flexibility of associating any DMA channel to
     * any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA
     * channel (like QDMA Channels).
     */
    unsigned short      dmaChPaRAMMapExists;

    /** Existence of memory protection feature */
    unsigned short      memProtectionExists;

    /** Base address of EDMA3 CC memory mapped registers. */
    void                *globalRegs;

    /** Base address of EDMA3 TCs memory mapped registers. */
    void                *tcRegs[EDMA3_MAX_TC];

    /**
     * EDMA3 transfer completion interrupt line (could be different for ARM
     * and DSP)
     */
    unsigned int        xferCompleteInt;

    /** EDMA3 CC error interrupt line (could be different for ARM and DSP) */
    unsigned int        ccError;

    /** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */
    unsigned int        tcError[EDMA3_MAX_TC];

    /**
     * \brief EDMA3 TC priority setting
     *
     * User can program the priority of the Event Queues
     * at a system-wide level.  This means that the user can set the
     * priority of an IO initiated by either of the TCs (Transfer Controllers)
     * relative to IO initiated by the other bus masters on the
     * device (ARM, DSP, USB, etc)
     */
    unsigned int        evtQPri [EDMA3_MAX_EVT_QUE];

    /**
     * \brief Event Queues Watermark Levels

     * To Configure the Threshold level of number of events
     * that can be queued up in the Event queues. EDMA3CC error register
     * (CCERR) will indicate whether or not at any instant of time the
     * number of events queued up in any of the event queues exceeds
     * or equals the threshold/watermark value that is set
     * in the queue watermark threshold register (QWMTHRA).
     */
    unsigned int        evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];

    /**
     * \brief Default Burst Size (DBS) of TCs.

     * An optimally-sized command is defined by the transfer controller
     * default burst size (DBS). Different TCs can have different
     * DBS values. It is defined in Bytes.
     */
    unsigned int        tcDefaultBurstSize[EDMA3_MAX_TC];

    /**
     * \brief Mapping from DMA channels to PaRAM Sets

     * If channel mapping exists (DCHMAP registers are present), this array
     * stores the respective PaRAM Set for each DMA channel. User can
     * initialize each array member with a specific PaRAM Set or with
     * EDMA3_DRV_CH_NO_PARAM_MAP.
     * If channel mapping doesn't exist, it is of no use as the EDMA3 RM
     * automatically uses the right PaRAM Set for that DMA channel.
     * Useful only if mapping exists, otherwise of no use.
     */
    unsigned int        dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];

     /**
      * \brief Mapping from DMA channels to TCCs
      *
      * This array stores the respective TCC (interrupt channel) for each
      * DMA channel. User can initialize each array member with a specific TCC
      * or with EDMA3_DRV_CH_NO_TCC_MAP. This specific
      * TCC code will be returned when the transfer is completed
      * on the mapped DMA channel.
      */
     unsigned int       dmaChannelTccMap [EDMA3_MAX_DMA_CH];

    /**
     * \brief Mapping from DMA channels to Hardware Events
     *
     * Each bit in this array corresponds to one DMA channel and tells whether
     * this DMA channel is tied to any peripheral. That is whether any
     * peripheral can send the synch event on this DMA channel or not.
     * 1 means the channel is tied to some peripheral; 0 means it is not.
     * DMA channels which are tied to some peripheral are RESERVED for that
     * peripheral only. They are not allocated when user asks for 'ANY' DMA
     * channel.
     * All channels need not be mapped, some can be free also.
     */
    unsigned int        dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
    } EDMA3_RM_GblConfigParams;



/**\struct  EDMA3_RM_InstanceInitConfig
 * \brief   Init-time Region Specific Configuration structure for
 * EDMA3 RM, to provide region specific Information.
 *
 * This configuration structure is used to specify which EDMA3 resources are
 * owned and reserved by the EDMA3 RM instance. This configuration
 * structure is shadow region specific and will be provided by the user at
 * run-time while calling EDMA3_RM_open ().
 *
 * Owned resources:
 * ****************
 *
 * EDMA3 RM Instances are tied to different shadow regions and hence different
 * masters. Regions could be:
 *
 * a) ARM,
 * b) DSP,
 * c) IMCOP (Imaging Co-processor) etc.
 *
 * User can assign each EDMA3 resource to a shadow region using this structure.
 * In this way, user specifies which resources are owned by the specific EDMA3
 * RM Instance.