📄 edma3_rm.h
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/** \file edma3_rm.h
\brief EDMA3 Controller Resource Manager Interface
This file contains Application Interface for the EDMA3 Controller
Resource Manager.
(C) Copyright 2006, Texas Instruments, Inc
\version 0.0.1 Purushotam Kumar - Created
0.1.0 Joseph Fernandez - Made generic
- Added documentation
- Moved SoC specific defines
to SoC specific header.
0.2.0 Anuj Aggarwal - Modified it for EDMA3 package
- Added multiple instances
capability
0.2.1 Anuj Aggarwal - Modified it for more run time
configuration.
- Made EDMA3 package OS
independent.
0.2.2 Anuj Aggarwal - Critical section handling code
modification. Uses semaphore and
interrupts disabling mechanism
for resource sharing.
0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
- IPR bit clearing in RM ISR
issue fixed.
- Sample application made generic
0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC
mapping, to fix QDMA missed
event issue.
0.3.2 Anuj Aggarwal - Added support for POLL mode
- Added a new API to modify the
CC Register.
1.0.0 Anuj Aggarwal - Fixed resource allocation related
bugs.
1.0.0.1 Anuj Aggarwal - Fixed spurious missed event
generation related bug.
1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC
compliant.
1.0.0.3 Anuj Aggarwal - Changed the directory structure
as per RTSC standard.
1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate
logical channels
b) Created EDMA3 config files
for different platforms
c) Misc changes
1.02.00.01 Anuj Aggarwal - a) Added DM6467 support
b) Fixed some MRs
1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files
b) IOCTL Interface added.
c) Fixed some MRs.
1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs.
b) Number of maximum Resource
Manager Instances is configurable.
c) Header files modified to have
extern "C" declarations.
*/
#ifndef _EDMA3_RM_H_
#define _EDMA3_RM_H_
/** Include common header file */
#include <ti/sdo/edma3/rm/edma3_common.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup Edma3RMIntrMgrMain EDMA3 Interrupt Manager Interface
*
* Top-level Encapsulation of documentation for EDMA3 Interrupt Manager Layer
*
* @{
*/
/**
* \defgroup Edma3RMIntrMgrInst Instance Wide Interface
*
* Instance Wide Interface of the EDMA3 Interrupt Manager Layer
*
* @{
*/
/**
* \defgroup Edma3RMStatus Completion status
*
* This group defines the error codes of completion
* of an EDMA3 transfer.
*
* @{
*/
/**\enum EDMA3_RM_TccStatus
* \brief This enum defines the channel specific status codes of
* an EDMA3 transfer. It is returned while calling the channel
* specific callback function to tell the status.
*/
typedef enum
{
/**
* DMA Transfer successfully completed (true completion mode)
* or submitted to the TC (early completion mode).
*/
EDMA3_RM_XFER_COMPLETE = 1,
/** Channel Controller has reported an error */
/**
* DMA missed events:- for all 64 DMA channels.
* These get latched in the event missed registers (EMR/EMRH).
*/
EDMA3_RM_E_CC_DMA_EVT_MISS = 2,
/**
* QDMA missed events:- for all QDMA channels.
* These get latched in the QDMA event missed register (QEMR).
*/
EDMA3_RM_E_CC_QDMA_EVT_MISS = 3
} EDMA3_RM_TccStatus;
/**\enum EDMA3_RM_GlobalError
* \brief This enum defines the global (not specific to any channel)
* error codes of completion of an EDMA3 transfer.
*/
typedef enum
{
/**
* Threshold exceed:- for all event queues.
* These get latched in EDMA3CC error register (CCERR).
* This error has a direct relation with the setting of
* EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl
*/
EDMA3_RM_E_CC_QUE_THRES_EXCEED = 1,
/**
* TCC error:- for outstanding transfer requests expected to return
* completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding
* the maximum limit of 63. This also gets latched in the CCERR.
*/
EDMA3_RM_E_CC_TCC = 2,
/** Transfer Controller has reported an error */
/**
* Detection of a Read error signaled by the source or destination address
*/
EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR = 3,
/**
* Detection of a Write error signaled by the source or destination address
*/
EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR = 4,
/**
* Attempt to read or write to an invalid address in the configuration
* memory map.
*/
EDMA3_RM_E_TC_INVALID_ADDR = 5,
/**
* Detection of a FIFO mode TR violating the FIFO mode transfer rules
* (the source/destination addresses and source/destination indexes must
* be aligned to 32 bytes).
*/
EDMA3_RM_E_TC_TR_ERROR = 6
} EDMA3_RM_GlobalError;
/* }@ Edma3RMStatus */
/**
* \brief Global Error callback - caters to module events like bus error etc
* which are not channel specific. Runs in ISR context.
*
* gblerrData is application provided data when open'ing the Resource Manager.
*/
typedef void (* EDMA3_RM_GblErrCallback)(EDMA3_RM_GlobalError deviceStatus,
unsigned int instanceId,
void *gblerrData);
/**\struct EDMA3_RM_GblErrCallbackParams
* \brief Global Error Callback parameters
*
* Consists of the Callback function and the data to be passed to it.
*/
typedef struct {
/**
* Instance wide callback function to catch non-channel specific errors.
*/
EDMA3_RM_GblErrCallback gblerrCb;
/** Application data to be passed back to the Global Error callback */
void *gblerrData;
} EDMA3_RM_GblErrCallbackParams;
/* @} Edma3RMIntrMgrInst */
/**
* \defgroup Edma3RMIntrMgrChannel Channel Specific Interface
*
* Channel Specific Interface of the EDMA3 Interrupt Manager Layer
*
* @{
*/
/**
* \brief TCC callback - caters to channel-specific events like
* "Event Miss Error" or "Transfer Complete". Runs in ISR context.
*
* appData is passed by the application during Register'ing of
* TCC Callback function.
*/
typedef void (* EDMA3_RM_TccCallback)(unsigned int tcc,
EDMA3_RM_TccStatus status,
void *appData);
/**
* \defgroup Edma3ResType Resource Type
*
* Resource Type part of the EDMA3 Resource Manager.
*
* @{
*/
/**\def EDMA3_RM_RES_ANY
* \brief Used to specify any available Resource Id (EDMA3_RM_ResDesc.resId)
*/
#define EDMA3_RM_RES_ANY (1010u)
/**\enum EDMA3_RM_ResType
* \brief EDMA3 Resource Type
*/
typedef enum
{
/** DMA Channel resource */
EDMA3_RM_RES_DMA_CHANNEL = 1,
/** QDMA Channel resource*/
EDMA3_RM_RES_QDMA_CHANNEL = 2,
/** TCC resource*/
EDMA3_RM_RES_TCC = 3,
/** Parameter RAM Set resource*/
EDMA3_RM_RES_PARAM_SET = 4
} EDMA3_RM_ResType;
/**\struct EDMA3_RM_ResDesc
* \brief Handle to a Resource.
*/
typedef struct
{
/** Resource Id */
/**
* Range of resId values :
* As an example, for resource Type = EDMA3_RM_RES_DMA_CHANNEL,
* resId can take values from 0 to EDMA3_MAX_DMA_CH
* Or
* resId can take the value EDMA3_RM_RES_ANY.
*/
unsigned int resId;
/** Resource Type */
EDMA3_RM_ResType type;
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