bios_edma3_drv_sample_c6455_cfg.c

vicp做为dm6446上的硬件加速器

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/** \file   bios_edma3_drv_sample_c6455_cfg.c

    \brief  SoC specific EDMA3 hardware related information like number of
            transfer controllers, various interrupt ids etc. It is used while
            interrupts enabling / disabling. It needs to be ported for different
             SoCs.

    (C) Copyright 2006, Texas Instruments, Inc

    \version    1.0   Anuj Aggarwal         - Created
                1.1   Anuj Aggarwal         - Made the sample app generic
                                            - Removed redundant arguments
                                              from Cache-related APIs
                                            - Added new function for Poll mode
                                              testing

 */

#include <ti/sdo/edma3/drv/edma3_drv.h>


/* c6455 Specific EDMA3 Information */

/** Number of Event Queues available */
#define EDMA3_NUM_EVTQUE                                4u

/** Number of Transfer Controllers available */
#define EDMA3_NUM_TC                                    4u

/** Interrupt no. for Transfer Completion */
#define EDMA3_CC_XFER_COMPLETION_INT                    72u

/** Interrupt no. for CC Error */
#define EDMA3_CC_ERROR_INT                              79u

/** Interrupt no. for TCs Error */
#define EDMA3_TC0_ERROR_INT                             81u
#define EDMA3_TC1_ERROR_INT                             82u
#define EDMA3_TC2_ERROR_INT                             83u
#define EDMA3_TC3_ERROR_INT                             84u
#define EDMA3_TC4_ERROR_INT                             0u
#define EDMA3_TC5_ERROR_INT                             0u
#define EDMA3_TC6_ERROR_INT                             0u
#define EDMA3_TC7_ERROR_INT                             0u

/**
* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
* ECM events (SoC specific). These ECM events come
* under ECM block XXX (handling those specific ECM events). Normally, block
* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
* is mapped to a specific HWI_INT YYY in the tcf file.
* Define EDMA3_HWI_INT to that specific HWI_INT YYY.
*/
#define EDMA3_HWI_INT                                   9u


/**
 * \brief Mapping of DMA channels 0-31 to Hardware Events from
 * various peripherals, which use EDMA for data transfer.
 * All channels need not be mapped, some can be free also.
 * 1: Mapped
 * 0: Not mapped
 *
 * This mapping will be used to allocate DMA channels when user passes
 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 * copy). The same mapping is used to allocate the TCC when user passes
 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 *
 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 */
#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          0xF013F007u
/**
 * \brief Mapping of DMA channels 32-63 to Hardware Events from
 * various peripherals, which use EDMA for data transfer.
 * All channels need not be mapped, some can be free also.
 * 1: Mapped
 * 0: Not mapped
 *
 * This mapping will be used to allocate DMA channels when user passes
 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 * copy). The same mapping is used to allocate the TCC when user passes
 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 *
 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 */
#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          0xFFFF3101u



/* Variable which will be used internally for referring number of Event Queues. */
unsigned int numEdma3EvtQue = EDMA3_NUM_EVTQUE;

/* Variable which will be used internally for referring number of TCs. */
unsigned int numEdma3Tc = EDMA3_NUM_TC;

/**
 * Variable which will be used internally for referring transfer completion
 * interrupt.
 */
unsigned int ccXferCompInt = EDMA3_CC_XFER_COMPLETION_INT;

/**
 * Variable which will be used internally for referring channel controller's
 * error interrupt.
 */
unsigned int ccErrorInt = EDMA3_CC_ERROR_INT;

/**
 * Variable which will be used internally for referring transfer controllers'
 * error interrupts.
 */
unsigned int tcErrorInt[8] =    {
                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT
                                };



/**
 * Variable which will be used internally for referring the hardware interrupt
 * for various EDMA3 interrupts.
 */
unsigned int hwInt = EDMA3_HWI_INT;


/* Driver Object Initialization Configuration */
EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams =
    {
    /** Total number of DMA Channels supported by the EDMA3 Controller */
    64u,
    /** Total number of QDMA Channels supported by the EDMA3 Controller */
    8u,
    /** Total number of TCCs supported by the EDMA3 Controller */
    64u,
    /** Total number of PaRAM Sets supported by the EDMA3 Controller */
    256u,
    /** Total number of Event Queues in the EDMA3 Controller */
    4u,
    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
    4u,
    /** Number of Regions on this EDMA3 controller */
    8u,

    /**
     * \brief Channel mapping existence
     * A value of 0 (No channel mapping) implies that there is fixed association
     * for a channel number to a parameter entry number or, in other words,
     * PaRAM entry n corresponds to channel n.
     */
    1u,

    /** Existence of memory protection feature */
    1u,

    /** Global Register Region of CC Registers */
    (void *)0x02A00000u,
    /** Transfer Controller (TC) Registers */
        {
        (void *)0x02A20000u,
        (void *)0x02A28000u,
        (void *)0x02A30000u,
        (void *)0x02A38000u,
        (void *)NULL,
        (void *)NULL,
        (void *)NULL,