📄 edma3.c
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}
}
else if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY)
{
/* First request for any available QDMA channel */
resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
resObj.resId = EDMA3_RM_RES_ANY;
result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
(EDMA3_RM_ResDesc *)&resObj);
if (result == EDMA3_DRV_SOK)
{
(*pLCh) = resObj.resId + EDMA3_DRV_QDMA_CH_MIN_VAL;
chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
/* Save the Resource Type for TCC registeration */
channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
}
else
{
result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
}
}
else if ((*pLCh) <= EDMA3_DRV_DMA_CH_MAX_VAL)
{
/* Request for a specific DMA channel */
resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
resObj.resId = *pLCh;
result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
if (result != EDMA3_RM_SOK)
{
result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;
}
else
{
mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];
if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP)
{
/*
* There is a PaRAM Set statically mapped to the returned
* channel number.
* This imposes a constraint on the PaRAM Set which we
* next request for.
* We update the PaRAM Set number with the one statically
* reserved for the afore-returned channel number.
*/
paRAMId = mappedPaRAMId;
}
chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
/* Save the Resource Type for TCC registeration */
channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
}
}
else if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL) && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))
{
/* Request for a specific QDMA channel */
resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
resObj.resId = (((*pLCh)) - EDMA3_DRV_QDMA_CH_MIN_VAL);
result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
if (result != EDMA3_RM_SOK)
{
result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
}
else
{
chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
/* Save the Resource Type for TCC registeration */
channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
}
}
else
{
result = EDMA3_DRV_E_INVALID_PARAM;
}
if (result == EDMA3_DRV_SOK)
{
/* Request for a PaRAM Set */
savedResType = resObj.type;
resObj.type = EDMA3_RM_RES_PARAM_SET;
resObj.resId = (unsigned int)paRAMId;
result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
paRAMId = (int)resObj.resId;
if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)
{
if (result == EDMA3_RM_SOK)
{
unsigned int linkCh = EDMA3_DRV_LINK_CH_MIN_VAL;
/*
* Search for the next Link channel handle available,
* starting from EDMA3_DRV_LINK_CH_MIN_VAL.
*/
while ((edma3DrvChBoundRes[drvObject->phyCtrllerInstId][linkCh].paRAMId != -1)
&& (linkCh <= EDMA3_DRV_LINK_CH_MAX_VAL))
{
/* Move to the next handle. */
linkCh++;
}
/* Verify the returned handle, it should lie in the correct range */
if (linkCh > EDMA3_DRV_LINK_CH_MAX_VAL)
{
result = EDMA3_DRV_E_INVALID_PARAM;
}
else
{
*pLCh = linkCh;
}
}
}
else
{
if (result != EDMA3_DRV_SOK)
{
/*
* Free the already allocated channel
* (only if channel is a Non-Link Channel)
*/
resObj.type = savedResType;
resObj.resId = *pLCh;
EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
}
else
{
/* Request for a TCC */
resObj.type = EDMA3_RM_RES_TCC;
if ((*pTcc) == EDMA3_DRV_TCC_ANY)
{
if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP)
{
resObj.resId = EDMA3_RM_RES_ANY;
}
else
{
resObj.resId = mappedTcc;
}
}
else
{
resObj.resId = *pTcc;
}
result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
if (result == EDMA3_DRV_SOK)
{
*pTcc = resObj.resId;
}
else
{
resObj.type = savedResType;
resObj.resId = *pLCh;
EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
resObj.type = EDMA3_RM_RES_PARAM_SET;
resObj.resId = (unsigned int)paRAMId;
EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
result = EDMA3_DRV_E_TCC_UNAVAIL;
}
if (result == EDMA3_DRV_SOK)
{
/* If callback function is not null, register it with the RM. */
if (NULL != tccCb)
{
/**
* Fill the resource id, whose associated TCC
* needs to be registered.
* For QDMA channels, pass the actual QDMA
* channel no instead of (*pLCh).
*/
if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)
&& ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))
{
channelObj.resId = (*pLCh) - EDMA3_DRV_QDMA_CH_MIN_VAL;
}
else
{
channelObj.resId = (*pLCh);
}
result = EDMA3_RM_registerTccCb (
drvInst->resMgrInstance,
(EDMA3_RM_ResDesc *)&channelObj,
*pTcc, tccCb, cbData);
if (result != EDMA3_DRV_SOK)
{
EDMA3_DRV_freeChannel (hEdma, *pLCh);
result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
}
}
if (result == EDMA3_DRV_SOK)
{
edma3OsProtectEntry(EDMA3_OS_PROTECT_INTERRUPT, &intState);
/* Associate Channel to Event Queue */
if ((*pLCh) < drvObject->gblCfgParams.numDmaChannels)
{
globalRegs->DMAQNUM[(*pLCh) >> 3u] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
globalRegs->DMAQNUM[(*pLCh) >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh),evtQueue);
}
else if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)
&& ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))
{
globalRegs->QDMAQNUM &=
EDMA3_DRV_QDMAQNUM_CLR_MASK((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL);
globalRegs->QDMAQNUM |=
EDMA3_DRV_QDMAQNUM_SET_MASK((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL,evtQueue);
}
edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState);
/**
* Map the allocated PaRAM Set to the logical
* DMa/QDMA channel.
*/
if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)
{
result = EDMA3_RM_mapQdmaChannel (drvInst->resMgrInstance,
((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL),
paRAMId,
EDMA3_RM_QDMA_TRIG_DEFAULT);
}
else
{
/**
* First check whether the mapping feature is supported on the underlying
* platform. In case it is not supported, dont call this API, because this
* API returns error in case the feature is not there.
*/
if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
{
result = EDMA3_RM_mapEdmaChannel (drvInst->resMgrInstance,
*pLCh,
paRAMId);
}
}
if (result != EDMA3_DRV_SOK)
{
EDMA3_DRV_freeChannel (hEdma, *pLCh);
result = EDMA3_DRV_E_CH_PARAM_BIND_FAIL;
}
else
{
/* Bind the resources PaRAM Set and TCC */
/* Set TCC of Param Set corresponding to specified paramId */
globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;
globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].tcc = *pTcc;
}
}
}
}
}
if (result == EDMA3_DRV_SOK)
{
/* Save the PaRAM Id and Trigger mode */
edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].paRAMId = paRAMId;
edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].trigMode =
EDMA3_DRV_TRIG_MODE_NONE;
/* Make the Link field NULL */
/* Get the Link-bcntReload PaRAM set entry */
linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +
(unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
/* Remove any linking */
linkBcntReld |= 0xFFFFu;
/* Store it back */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
+ (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
/*
* For QDMA channels, Enable the transfer.
* So that user doesn't have to call EDMA3_DRV_enableTransfer() again.
*/
if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)
&& ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))
{
drvInst->shadowRegs->QEESR = (1u<<((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL));
/* save the trigger mode for future use */
edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
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