edma3.h

vicp做为dm6446上的硬件加速器

#define EDMA3_DRV_CCNT_MAX_VAL              (0xFFFFu)
/** Max value of BCntReld */
#define EDMA3_DRV_BCNTRELD_MAX_VAL          (0xFFFFu)
/** Max value of SrcBIdx */
#define EDMA3_DRV_SRCBIDX_MAX_VAL           (0x7FFF)
/** Min value of SrcBIdx */
#define EDMA3_DRV_SRCBIDX_MIN_VAL           (-32768)
/** Max value of SrcCIdx */
#define EDMA3_DRV_SRCCIDX_MAX_VAL           (0x7FFF)
/** Min value of SrcCIdx */
#define EDMA3_DRV_SRCCIDX_MIN_VAL           (-32768)
/** Max value of DestBIdx */
#define EDMA3_DRV_DSTBIDX_MAX_VAL           (0x7FFF)
/** Min value of DestBIdx */
#define EDMA3_DRV_DSTBIDX_MIN_VAL           (-32768)
/** Max value of DestCIdx */
#define EDMA3_DRV_DSTCIDX_MAX_VAL           (0x7FFF)
/** Min value of DestCIdx */
#define EDMA3_DRV_DSTCIDX_MIN_VAL           (-32768)
/** Max value of Queue Priority */
#define EDMA3_DRV_QPRIORITY_MAX_VAL         (7u)
/** Min value of Queue Priority */
#define EDMA3_DRV_QPRIORITY_MIN_VAL         (0u)




/**
 * \defgroup Edma3DrvIntBoundVals Boundary Values
 *
 * Boundary Values for Logical Channel Ranges
 *
 * @{
 */
/** Max of DMA Channels */
#define EDMA3_DRV_DMA_CH_MAX_VAL        (EDMA3_MAX_DMA_CH - 1u)

/** Min of Link Channels */
#define EDMA3_DRV_LINK_CH_MIN_VAL       (EDMA3_MAX_DMA_CH)

/** Max of Link Channels */
#define EDMA3_DRV_LINK_CH_MAX_VAL       (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u)

/** Min of QDMA Channels */
#define EDMA3_DRV_QDMA_CH_MIN_VAL       (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)

/** Max of QDMA Channels */
#define EDMA3_DRV_QDMA_CH_MAX_VAL       (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u)

/** Max of Logical Channels */
#define EDMA3_DRV_LOG_CH_MAX_VAL       (EDMA3_DRV_QDMA_CH_MAX_VAL)


/* @} Edma3DrvIntBoundVals */


/**
 * \defgroup Edma3DrvIntObjMaint Object Maintenance
 *
 * Maintenance of the EDMA3 Driver Object
 *
 * @{
 */
/** To maintain the state of the EDMA3 Driver object */
typedef enum {
    /** Object deleted */
    EDMA3_DRV_DELETED   = 0,
    /** Obect Created */
    EDMA3_DRV_CREATED   = 1,
    /** Object Opened */
    EDMA3_DRV_OPENED    = 2,
    /** Object Closed */
    EDMA3_DRV_CLOSED    = 3
} EDMA3_DRV_ObjState;


 /**
 * \brief EDMA3 Driver Object (HW Specific) Maintenance structure.
 *
 * Used to maintain information of the EDMA3 HW configuration
 * thoughout the lifetime of the EDMA3 Driver Object,
 * one for each EDMA3 hardware instance.
 *
 */
typedef struct
    {
    /** Physical Instance ID of EDMA3 Controller */
    unsigned int            phyCtrllerInstId;

    /** State information of the EDMA3 Driver object */
    EDMA3_DRV_ObjState      state;

    /** Number of EDMA3 Driver instances */
    unsigned int            numOpens;

    /**
     * \brief Init-time Configuration structure for EDMA3
     * controller, to provide Global SoC specific Information.
     *
     * This configuration info can be provided by the user at run-time,
     * while calling EDMA3_DRV_create(). If not provided at run-time,
     * this info will be taken from the config file edma3Cfg.c.
     */
    EDMA3_DRV_GblConfigParams gblCfgParams;

} EDMA3_DRV_Object;


/**
 * \brief EDMA3 Driver Instance Configuration Structure.
 *
 * Used to maintain information of the EDMA3 Driver Instances.
 * One such storage exists for each instance of the EDMA3 Driver.
 * There could be as many Driver Instances as there are shadow
 * regions. Multiple EDMA3 Driver instances on the same shadow
 * region are NOT allowed.
 */
typedef struct
    {
    /** Region Identification */
    EDMA3_RM_RegionId       regionId;

    /**
     * Whether EDMA3 driver instance is Master or not.
     * Only the master instance shadow region will receive the
     * EDMA3 interrupts, if enabled.
     */
    unsigned short          isMaster;

    /**
     * EDMA3 Driver Instance (Shadow Region) specific
     * init configuration.
     * If NULL, static values will be taken
     */
    EDMA3_DRV_InstanceInitConfig    drvInstInitConfig;


    /** EDMA3 Driver Instance specific semaphore handle */
    void                    *drvSemHandle;

    /** Instance wide Global Error callback parameters */
    EDMA3_RM_GblErrCallbackParams   gblerrCbParams;

    /** Pointer to appropriate Shadow Register region of CC Registers */
    EDMA3_CCRL_ShadowRegs           *shadowRegs;

    /**
     * Pointer to the EDMA3 Driver Object, for HW specific / Global
     * Information.
     */
    EDMA3_DRV_Object                *pDrvObjectHandle;

    /** Pointer to the Resource Manager Instance opened by the EDMA3 Driver */
    EDMA3_RM_Handle                 resMgrInstance;

    }EDMA3_DRV_Instance;


/* @} Edma3DrvIntObjMaint */


/**
 * \brief EDMA3 Channel-Bound resources.
 *
 * Used to maintain information of the EDMA3 resources
 * (specifically Parameter RAM set and TCC) and the mode of triggering
 * transfer (Manual, HW event driven etc) bound to the
 * particular channel within EDMA3_DRV_requestChannel().
 */
typedef struct {
    /** PaRAM Set number associated with the particular channel */
    int paRAMId;

    /** TCC associated with the particular channel */
    unsigned int tcc;

    /** Mode of triggering transfer */
    EDMA3_DRV_TrigMode trigMode;

} EDMA3_DRV_ChBoundResources;


/**
 * \brief EDMA3 Channel Type
 */
typedef enum
{
    /** Invalid Channel */
    EDMA3_DRV_CHANNEL_TYPE_NONE,

    /** DMA Channel */
    EDMA3_DRV_CHANNEL_TYPE_DMA      = 1,

    /** QDMA Channel */
    EDMA3_DRV_CHANNEL_TYPE_QDMA     = 2,

    /** LINK Channel */
    EDMA3_DRV_CHANNEL_TYPE_LINK     = 3

} EDMA3_DRV_ChannelType;

#ifdef __cplusplus
}
#endif /* extern "C" */

/* @} Edma3DrvInt */
#endif         /* _EDMA3_H_ */