📄 edma3.h
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**| Copyright (c) 1998-2006 Texas Instruments Incorporated |**
**| ALL RIGHTS RESERVED |**
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/** \file edma3.h
\brief EDMA3 Driver Internal header file.
This file contains implementation specific details used by the EDMA3
Driver internally.
(C) Copyright 2006, Texas Instruments, Inc
\version 0.1.0 Joseph Fernandez - Created
0.2.0 Anuj Aggarwal - Modified it for EDMA3 package
- Added multiple instances
capability
0.2.1 Anuj Aggarwal - Modified it for more run time
configuration.
- Made EDMA3 package OS
independent.
0.2.2 Anuj Aggarwal - Critical section handling code
modification. Uses semaphore and
interrupts disabling mechanism
for resource sharing.
0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
- IPR bit clearing in RM ISR
issue fixed.
- Sample application made generic
0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC
mapping, to fix QDMA missed
event issue.
0.3.2 Anuj Aggarwal - Added support for POLL mode
- Added a new API to modify the
CC Register.
1.0.0 Anuj Aggarwal - Fixed resource allocation related
bugs.
1.0.0.1 Anuj Aggarwal - Fixed spurious missed event
generation related bug.
1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC
compliant.
1.0.0.3 Anuj Aggarwal - Changed the directory structure
as per RTSC standard.
1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate
logical channels
b) Created EDMA3 config files
for different platforms
c) Misc changes
1.02.00.01 Anuj Aggarwal - a) Added DM6467 support
b) Fixed some MRs
1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files
b) IOCTL Interface added.
c) Fixed some MRs.
1.04 Anuj Aggarwal - a) Header files modified to have
extern "C" declarations.
b) Implemented ECNs DPSP00009815
& DPSP00010035.
*/
#ifndef _EDMA3_H_
#define _EDMA3_H_
/** Include EDMA3 Driver header file */
#include <ti/sdo/edma3/drv/edma3_drv.h>
/* For the EDMA3 CC Register Layer functionality */
#include <ti/sdo/edma3/rm/src/edma3_rl_cc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup Edma3DrvInt Internal Interface Definition for EDMA3 Driver
*
* Documentation of the Internal Interface of EDMA3 Driver
*
* @{
*/
/* Mask defines */
/** Parameter RAM Set field OPT bit-field defines */
/** OPT-SAM bit Clear */
#define EDMA3_DRV_OPT_SAM_CLR_MASK (~EDMA3_CCRL_OPT_SAM_MASK)
/** OPT-SAM bit Set */
#define EDMA3_DRV_OPT_SAM_SET_MASK(mode) (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)
/** OPT-DAM bit Clear */
#define EDMA3_DRV_OPT_DAM_CLR_MASK (~EDMA3_CCRL_OPT_DAM_MASK)
/** OPT-DAM bit Set */
#define EDMA3_DRV_OPT_DAM_SET_MASK(mode) (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)
/** OPT-SYNCDIM bit Clear */
#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK (~EDMA3_CCRL_OPT_SYNCDIM_MASK)
/** OPT-SYNCDIM bit Set */
#define EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype) (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)
/** OPT-STATIC bit Clear */
#define EDMA3_DRV_OPT_STATIC_CLR_MASK (~EDMA3_CCRL_OPT_STATIC_MASK)
/** OPT-STATIC bit Set */
#define EDMA3_DRV_OPT_STATIC_SET_MASK(en) (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)
/** OPT-FWID bitfield Clear */
#define EDMA3_DRV_OPT_FWID_CLR_MASK (~EDMA3_CCRL_OPT_FWID_MASK)
/** OPT-FWID bitfield Set */
#define EDMA3_DRV_OPT_FWID_SET_MASK(width) (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)
/** OPT-TCCMODE bit Clear */
#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK (~EDMA3_CCRL_OPT_TCCMODE_MASK)
/** OPT-TCCMODE bit Set */
#define EDMA3_DRV_OPT_TCCMODE_SET_MASK(early) (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)
/** OPT-TCC bitfield Clear */
#define EDMA3_DRV_OPT_TCC_CLR_MASK (~EDMA3_CCRL_OPT_TCC_MASK)
/** OPT-TCC bitfield Set */
#define EDMA3_DRV_OPT_TCC_SET_MASK(tcc) (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
/** OPT-TCINTEN bit Clear */
#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_TCINTEN_MASK)
/** OPT-TCINTEN bit Set */
#define EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten) (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)
/** OPT-ITCINTEN bit Clear */
#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCINTEN_MASK)
/** OPT-ITCINTEN bit Set */
#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten) (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)
/** OPT-TCCHEN bit Clear */
#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_TCCHEN_MASK)
/** OPT-TCCHEN bit Set */
#define EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen) (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)
/** OPT-ITCCHEN bit Clear */
#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCCHEN_MASK)
/** OPT-ITCCHEN bit Set */
#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen) (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
/** OPT-SAM bit Get */
#define EDMA3_DRV_OPT_SAM_GET_MASK(mode) ((mode)&1u)
/** OPT-DAM bit Get */
#define EDMA3_DRV_OPT_DAM_GET_MASK(mode) (((mode)&(1u<<1u))>>1u)
/** OPT-SYNCDIM bit Get */
#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype) (((synctype)&(1u<<2u))>>2u)
/** OPT-STATIC bit Get */
#define EDMA3_DRV_OPT_STATIC_GET_MASK(en) (((en)&(1u<<3u))>>3u)
/** OPT-FWID bitfield Get */
#define EDMA3_DRV_OPT_FWID_GET_MASK(width) (((width)&(0x7u<<8u))>>8u)
/** OPT-TCCMODE bit Get */
#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early) (((early)&(1u<<11u))>>11u)
/** OPT-TCC bitfield Get */
#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc) (((tcc)&(0x3fu<<12u))>>12u)
/** OPT-TCINTEN bit Get */
#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten) (((tcinten)&(1u<<20u))>>20u)
/** OPT-ITCINTEN bit Get */
#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten) (((itcinten)&(1u<<21u))>>21u)
/** OPT-TCCHEN bit Get */
#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen) (((tcchen)&(1u<<22u))>>22u)
/** OPT-ITCCHEN bit Get */
#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen) (((itcchen)&(1u<<23u))>>23u)
/** DMAQNUM bits Clear */
#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum) (~(0x7u<<(((chNum)%8u)*4u)))
/** DMAQNUM bits Set */
#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum,queNum) ((0x7u & (queNum)) << (((chNum)%8u)*4u))
/** QDMAQNUM bits Clear */
#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum) (~(0x7u<<((chNum)*4u)))
/** QDMAQNUM bits Set */
#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum,queNum) ((0x7u & (queNum)) << ((chNum)*4u))
/* Other Mask defines */
/** QCHMAP-TrigWord bitfield Clear */
#define EDMA3_DRV_QCH_TRWORD_CLR_MASK (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
/** QCHMAP-TrigWord bitfield Set */
#define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId) (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
/** Max value of ACnt */
#define EDMA3_DRV_ACNT_MAX_VAL (0xFFFFu)
/** Max value of BCnt */
#define EDMA3_DRV_BCNT_MAX_VAL (0xFFFFu)
/** Max value of CCnt */
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