📄 edma3_drv.h
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EDMA3_DRV_W8BIT);
- result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
- result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
- result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
ccnt, bcntreload, synctype);
- Link both the channels
- result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);
- Enable the final completion interrupts on both the channels
- result = EDMA3_DRV_setOptField (hEdma, ch1Id,
EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
- result = EDMA3_DRV_setOptField (hEdma, ch2Id,
EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
- Enable the transfer on channel 1.
- result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
EDMA3_DRV_TRIG_MODE_MANUAL);
- Wait for the completion interrupt on Ch1 and then enable the
transfer again for the LINK channel, to provide the required
sync event.
- result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
EDMA3_DRV_TRIG_MODE_MANUAL);
- Note: Enabling of transfers on channel 1 (for master and link
channel) is required as many number of times as the sync events
are required. For ASync mode, number of sync events=(bcnt * ccnt)
and for ABSync mode, number of sync events = ccnt.
- Use Case 3: Memory to memory transfer on any available
- QDMA Channel\n\n
- qTcc1 = EDMA3_DRV_TCC_ANY;
- qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
- result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
(EDMA3_RM_EventQueue)0, &callback1, NULL);
- Set the QDMA trigger word.
- result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
EDMA3_RM_QDMA_TRIG_DST);
- Note: DONOT write the destination address (trigger word) before
completing the configuration as it will trigger the
transfer. Also, DONOT use EDMA3_DRV_setDestParams() to set
the destination address as it also sets other parameters.
Use EDMA3_DRV_setPaRAMEntry() to set the destination address
- result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
(unsigned int)(srcBuff1),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT);
- Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,
SyncType)
acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
synctype = EDMA3_DRV_SYNC_A;
- result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
ccnt, bcntreload, synctype);
- srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
- result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
- result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
- Enable the final completion interrupt.
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
- Set the Destination Addressing Mode as Increment
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
EDMA3_DRV_OPT_FIELD_DAM,
EDMA3_DRV_ADDR_MODE_INCR);
- Trigger the QDMA channel by writing the destination address
- result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
EDMA3_DRV_PARAM_ENTRY_DST,
(unsigned int)(dstBuff1));
-
- Use Case 4: Linked memory to memory transfer on any available
- QDMA Channel\n\n
- Setup for any QDMA Channel
- qTcc1 = EDMA3_DRV_TCC_ANY;
- qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
- result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
(EDMA3_RM_EventQueue)0, &callback1, NULL);
- Setup for Channel 2
- qCh2Id = EDMA3_DRV_LINK_CHANNEL;
- qTcc2 = EDMA3_DRV_TCC_ANY;
- result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2,
(EDMA3_RM_EventQueue)0,
&callback2, NULL);
- result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id,
(unsigned int)(srcBuff2),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT);
- result = EDMA3_DRV_setDestParams(hEdma, qCh2Id,
(unsigned int)(dstBuff2),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT);
- acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
synctype = EDMA3_DRV_SYNC_A;
- result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,
ccnt, BRCnt,
EDMA3_DRV_SYNC_A);
- srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
- result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);
- result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);
- result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
- Make the PaRAM Set associated with qCh2Id as Static
- result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
EDMA3_DRV_OPT_FIELD_STATIC, 1u);
- Link both the channels
- result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id);
- Set the QDMA trigger word.
- result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
EDMA3_DRV_QDMA_TRIG_DST);
- Note: DONOT write the destination address (trigger word) before
completing the configuration as it'll trigger the transfer.
Also, DONOT use EDMA3_DRV_setDestParams () function to set
the destination address as it also sets other parameters.
Use EDMA3_DRV_setPaRAMEntry() to set the dest address.
- result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
(unsigned int)(srcBuff1),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT);
- Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,
SyncType)
acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
synctype = EDMA3_DRV_SYNC_A;
- result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
ccnt, bcntreload, synctype);
- srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
- result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
- result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
- Set the Destination Addressing Mode as Increment
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
EDMA3_DRV_OPT_FIELD_DAM,
EDMA3_DRV_ADDR_MODE_INCR);
- Trigger the QDMA channel by writing the destination address
- result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
EDMA3_DRV_PARAM_ENTRY_DST,
(unsigned int)(dstBuff1));
*/
/* @} Edma3DrvUsage */
/*---------------------------------------------------------------------------*/
/*------------------Usage Guidelines End-------------------------------------*/
/*---------------------------------------------------------------------------*/
/**
* \defgroup Edma3DrvErrorCode EDMA3 Driver Error Codes
*
* Error Codes returned by the EDMA3 Driver
*
* @{
*/
/** EDMA3 Driver Error Codes Base define */
#define EDMA3_DRV_E_BASE (-128)
/**
* EDMA3 Driver Object Not Deleted yet.
* So it cannot be created.
*/
#define EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE)
/**
* EDMA3 Driver Object Not Closed yet.
* So it cannot be deleted.
*/
#define EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1)
/**
* EDMA3 Driver Object Not Opened yet
* So it cannot be closed.
*/
#define EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2)
/**
* While closing EDMA3 Driver, Resource Manager
* Close Failed.
*/
#define EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3)
/** The requested DMA Channel not available */
#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4)
/** The requested QDMA Channel not available */
#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5)
/** The requested PaRAM Set not available */
#define EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6)
/** The requested TCC not available */
#define EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7)
/** The registration of TCC failed */
#define EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8)
/** The binding of Channel and PaRAM Set failed */
#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9)
/**
* The address of the memory location passed as argument
* is not properly aligned. It should be 32 bytes aligned.
*/
#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10)
/** Invalid Parameter passed to API */
#define EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11)
/** Invalid State of EDMA3 HW Obj */
#define EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12)
/** EDMA3 Driver instance already exists for the specified region */
#define EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13)
/** FIFO width not supported by the requested TC */
#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14)
/** Semaphore related error */
#define EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15)
/* @} Edma3DrvErrorCode */
/**
* This define is used to specify that a DMA channel is NOT tied to any PaRAM
* Set and hence any available PaRAM Set could be used for that DMA channel.
* It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global
* configuration structure EDMA3_RM_GblConfigParams.
*
* This value should mandatorily be used to mark DMA channels with no initial
* mapping to specific PaRAM Sets.
*/
#define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP
/**
* This define is used to specify that the DMA/QDMA channel is not tied to any
* TCC and hence any available TCC could be used for that DMA/QDMA channel.
* It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global
* configuration structure EDMA3_RM_GblConfigParams.
*
* This value should mandatorily be used to mark DMA channels with no initial
* mapping to specific TCCs.
*/
#define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP
/**\struct EDMA3_DRV_GblConfigParams
* \brief Init-time Configuration structure for EDMA3
* controller, to provide Global SoC specific Information.
*
* This configuration structure is used to specify the EDMA3 Driver
* global settings, specific to the SoC. For e.g. number of DMA/QDMA channels,
* number of PaRAM sets, TCCs, event queues, transfer controllers, base
* addresses of CC global registers and TC registers, interrupt number for
* EDMA3 transfer completion, CC error, event queues' priority, watermark
* threshold level etc.
* This configuration information is SoC specific and could be provided by the
* user at run-time while creating the EDMA3 Driver Object, using API
* EDMA3_DRV_create. In case user doesn't provide it, this information could be
* taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in
* case it is available.
*/
typedef struct {
/** Number of DMA Channels supported by the underlying EDMA3 Controller. */
unsigned int numDmaChannels;
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