📄 csl2_dat.c
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if (EDMA3_DRV_SOK != EDMA3_DRV_setPaRAM(DAT_EDMA3LLD_hEdma, chNum,
newPaRAM)) {
printf("Error setting up transfer \n");
HWI_enable();
return INVALID_ID;
}
*/
return _setupTransferOptions(chNum, tccNum);
}
/*
* ======== DAT_copy2d =========
* 2-dimensional copy from src to dst of lineCnt lines each of length lineLen
* bytes. The pitch for the second dimension is linePitch bytes
*/
Uint32 DAT_copy2d(Uint32 type, void *src, void *dst, Uint16 lineLen,
Uint16 lineCnt, Uint16 linePitch) {
Uint32 chNum = 0;
Uint32 tccNum = 0;
/*
* Obtain a free channel
*/
chNum = _getFreeChannel(&tccNum);
/*
* Set up Transfer Paramters for this channel
*/
EDMA3_DRV_setSrcParams(DAT_EDMA3LLD_hEdma, chNum, (unsigned int)src,
EDMA3_DRV_ADDR_MODE_INCR,(EDMA3_DRV_FifoWidth)0);
EDMA3_DRV_setDestParams(DAT_EDMA3LLD_hEdma, chNum, (unsigned int)dst,
EDMA3_DRV_ADDR_MODE_INCR,(EDMA3_DRV_FifoWidth)0);
EDMA3_DRV_setTransferParams(DAT_EDMA3LLD_hEdma, chNum, lineLen, lineCnt,
1, 0, EDMA3_DRV_SYNC_AB);
/*
* Depending on type of transfer set the src and dest BIdx
* Different types of transfers differ only in the Src and Dst BIdx-es
*/
switch (type) {
case DAT_1D2D:
EDMA3_DRV_setSrcIndex(DAT_EDMA3LLD_hEdma, chNum, lineLen, 0);
EDMA3_DRV_setDestIndex(DAT_EDMA3LLD_hEdma, chNum, linePitch, 0);
break;
case DAT_2D1D:
EDMA3_DRV_setSrcIndex(DAT_EDMA3LLD_hEdma, chNum, linePitch, 0);
EDMA3_DRV_setDestIndex(DAT_EDMA3LLD_hEdma, chNum, lineLen, 0);
break;
case DAT_2D2D:
EDMA3_DRV_setSrcIndex(DAT_EDMA3LLD_hEdma, chNum, linePitch, 0);
EDMA3_DRV_setDestIndex(DAT_EDMA3LLD_hEdma, chNum, linePitch, 0);
break;
}
return _setupTransferOptions(chNum, tccNum);
}
/*
* ======== DAT_fill =========
* Fills up dst with byteCnt bytes of the pattern pointed to be 'value'
*/
Uint32 DAT_fill(void *dst, Uint16 byteCnt, Uint32 *value) {
Uint32 chNum = 0;
Uint32 tccNum = 0;
/*
* Obtain a free channel
*/
chNum = _getFreeChannel(&tccNum);
/*
* Set up Transfer Paramters for this channel
* For DAT_fill, the SrcIndex is set to zero since src address never changes
*/
EDMA3_DRV_setSrcParams(DAT_EDMA3LLD_hEdma, chNum, (unsigned int )value,
EDMA3_DRV_ADDR_MODE_INCR,(EDMA3_DRV_FifoWidth)0);
EDMA3_DRV_setDestParams(DAT_EDMA3LLD_hEdma, chNum, (unsigned int)dst,
EDMA3_DRV_ADDR_MODE_INCR,(EDMA3_DRV_FifoWidth)0);
EDMA3_DRV_setTransferParams(DAT_EDMA3LLD_hEdma, chNum, 8, byteCnt>>3 ,1,0,
EDMA3_DRV_SYNC_AB);
EDMA3_DRV_setSrcIndex(DAT_EDMA3LLD_hEdma, chNum, 0, 0);
EDMA3_DRV_setDestIndex(DAT_EDMA3LLD_hEdma, chNum, 8, 0);
return _setupTransferOptions(chNum, tccNum);
}
/*
* ======== DAT_wait =========
* Wait for the transfer identified by waitId, to complete
*/
void DAT_wait(Uint32 waitId) {
/*
* If both the registers are zero, we're done !!
*/
if (0x0 == (TransferCompleteL | TransferCompleteH)) {
return;
}
/*
* Check if we need to wait for all transfers or just this one ?
*/
if (DAT_XFRID_WAITALL == waitId) {
/* If for all, then use both the TransferComplete register for checking
* if transfer has completed
*/
while (1) {
if (0x0 == (TransferCompleteH | TransferCompleteL) ) {
return;
}
}
}
/*
* Use the waitId to check for transfers having completed
* Check for that bit in the completion register in a loop
*/
if (waitId < 32) {
while(1) {
if (0x0 == GET_REGISTER32_BIT(TransferCompleteL, waitId)) {
return;
}
}
}
else {
waitId = waitId -32;
while(1) {
if (0x0 == GET_REGISTER32_BIT(TransferCompleteH,waitId)) {
return;
}
}
}
}
/*
* ======== DAT_busy =========
* Check the busy status of transfer identified by waitId
*/
int DAT_busy(Uint32 waitId) {
/*
* Check if the particular transfer has completed by returning the status
* from the itnernal completion register
*/
if (waitId < 32) {
return GET_REGISTER32_BIT(TransferCompleteL,waitId);
}
else {
return GET_REGISTER32_BIT(TransferCompleteH, waitId-32);
}
}
/*
* static function definitions
*/
/*
* ======== _getFreeChannel =========
* Used to obtain the next available channel to set up a new transfer
* Function spins till a channel becomes available
*/
static inline Uint32 _getFreeChannel(Uint32 *tccNum) {
Uint32 chNum,index ;
/*
* Start looking for available channels from the index after the one
* that was allocated previously
*/
index = (lastAllocatedIndex + 1)%(DAT_EDMA3LLD_numAllocatedChannels);
/*
* Spins till a free bit in TransferComplete is found
*/
while (1) {
*tccNum = DAT_allocatedChannels[index].tccNo;
if (*tccNum < 32) {
if((GET_REGISTER32_BIT(TransferCompleteL,*tccNum)) == 0) {
chNum = DAT_allocatedChannels[index].paramNo;
lastAllocatedIndex = index;
return chNum;
}
}
else {
if((GET_REGISTER32_BIT(TransferCompleteH,*tccNum - 32)) == 0) {
chNum = DAT_allocatedChannels[index].paramNo;
lastAllocatedIndex = index;
return chNum;
}
}
/*
* Increment index
*/
index = (index + 1)%(DAT_EDMA3LLD_numAllocatedChannels);
}
}
/*
* ======== _transferComplete =========
* Callback function for transfer completion on a particular channel
*/
static void _transferComplete(Uint32 tccNum, EDMA3_RM_TccStatus status,
void *param) {
int i;
(void)param;
/*
* Check for errors, print error message, clear error bits and return
*/
if (EDMA3_RM_XFER_COMPLETE != status)
{
printf("Error during transfer, clearing Missed Event Register\n");
for (i = 0; i < DAT_EDMA3LLD_numAllocatedChannels ;i++)
{
if (tccNum == DAT_allocatedChannels[i].tccNo)
{
EDMA3_DRV_clearErrorBits(DAT_EDMA3LLD_hEdma, DAT_allocatedChannels[i].paramNo);
return;
}
}
}
/*
* Mark zero in bit position tccNum
*/
if (tccNum < 32) {
CLEAR_REGISTER32_BIT(TransferCompleteL, tccNum );
}
else {
CLEAR_REGISTER32_BIT(TransferCompleteH, tccNum -32 );
}
}
/*
* ======== _setupTransferOptions =========
* Function to set up the OPT for given chNum and tccNum
*/
inline Uint32 _setupTransferOptions(Uint32 chNum, Uint32 tccNum) {
/*
* Set up OPT for this transfer
*/
EDMA3_DRV_setOptField(DAT_EDMA3LLD_hEdma, chNum, EDMA3_DRV_OPT_FIELD_SAM,
0x0);
EDMA3_DRV_setOptField(DAT_EDMA3LLD_hEdma, chNum, EDMA3_DRV_OPT_FIELD_DAM,
0x0);
EDMA3_DRV_setOptField(DAT_EDMA3LLD_hEdma, chNum, EDMA3_DRV_OPT_FIELD_STATIC,
0x1);
EDMA3_DRV_setOptField(DAT_EDMA3LLD_hEdma, chNum,
EDMA3_DRV_OPT_FIELD_TCCMODE, 0x0);
EDMA3_DRV_setOptField (DAT_EDMA3LLD_hEdma, chNum,
EDMA3_DRV_OPT_FIELD_TCINTEN, 0x1);
/*
* Set a 1 bit in the TransferComplete register corresponding to the tcc
*/
if (tccNum < 32) {
SET_REGISTER32_BIT(TransferCompleteL,tccNum);
}
else {
SET_REGISTER32_BIT(TransferCompleteH,tccNum - 32);
}
/*
* Clear error bits before starting transfer
*/
EDMA3_DRV_clearErrorBits(DAT_EDMA3LLD_hEdma, chNum);
/*
* Enable transfer
*/
if (EDMA3_DRV_SOK != EDMA3_DRV_enableTransfer(DAT_EDMA3LLD_hEdma,chNum,
EDMA3_DRV_TRIG_MODE_MANUAL)) {
printf("Error enabling transfer \n");
if (tccNum < 32) {
CLEAR_REGISTER32_BIT(TransferCompleteL,tccNum);
}
else {
CLEAR_REGISTER32_BIT(TransferCompleteH,tccNum - 32);
}
return DAT_INVALID_ID;
}
return tccNum;
}
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