📄 spi_test_save.lst
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A51 MACRO ASSEMBLER SPI_TEST_SAVE 04/26/2009 16:17:21 PAGE 1
MACRO ASSEMBLER A51 V8.00
OBJECT MODULE PLACED IN SPI_TEST_Save.OBJ
ASSEMBLER INVOKED BY: C:\SiLabs\MCU\IDEfiles\C51\BIN\a51.exe SPI_TEST_Save.asm XR GEN DB EP NOMOD51
LOC OBJ LINE SOURCE
1
2
3
4 ;$include (C8051F310.inc)
+1 5 ;---------------------------------------------------------------------------
+1 6 ;
+1 7 ;
+1 8 ;
+1 9 ;
+1 10 ; FILE NAME : C8051F310.INC
+1 11 ; TARGET MCUs : C8051F310, 'F311
+1 12 ; DESCRIPTION : Register/bit definitions for the C8051F31x product family.
+1 13 ;
+1 14 ; REVISION 1.3
+1 15 ; -- added ESPI0 and PSPI0
+1 16 ; REVISION 1.2
+1 17 ; -- added VDM0CN (0xff)
+1 18 ;
+1 19 ; REVISION 1.1
+1 20 ; -- changed TARGET MCUs to 'F310, 'F311
+1 21 ; -- SPICFG --> SPI0CFG
+1 22 ; -- SPICKR --> SPI0CKR
+1 23 ; -- SPIDAT --> SPI0DAT
+1 24 ; -- removed CLKMUL (0xb9)
+1 25 ; -- AMUX0N --> AMX0N
+1 26 ; -- AMUX0P --> AMX0P
+1 27 ;
+1 28 ;---------------------------------------------------------------------------
+1 29
+1 30 ; BYTE Registers
0080 +1 31 P0 DATA 080H ; PORT 0
0081 +1 32 SP DATA 081H ; STACK POINTER
0082 +1 33 DPL DATA 082H ; DATA POINTER - LOW BYTE
0083 +1 34 DPH DATA 083H ; DATA POINTER - HIGH BYTE
0087 +1 35 PCON DATA 087H ; POWER CONTROL
0088 +1 36 TCON DATA 088H ; TIMER CONTROL
0089 +1 37 TMOD DATA 089H ; TIMER MODE
008A +1 38 TL0 DATA 08AH ; TIMER 0 - LOW BYTE
008B +1 39 TL1 DATA 08BH ; TIMER 1 - LOW BYTE
008C +1 40 TH0 DATA 08CH ; TIMER 0 - HIGH BYTE
008D +1 41 TH1 DATA 08DH ; TIMER 1 - HIGH BYTE
008E +1 42 CKCON DATA 08EH ; CLOCK CONTROL
008F +1 43 PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL
0090 +1 44 P1 DATA 090H ; PORT 1
0091 +1 45 TMR3CN DATA 091H ; TIMER 3 CONTROL
0092 +1 46 TMR3RLL DATA 092H ; TIMER 3 RELOAD LOW
0093 +1 47 TMR3RLH DATA 093H ; TIMER 3 RELOAD HIGH
0094 +1 48 TMR3L DATA 094H ; TIMER 3 LOW BYTE
0095 +1 49 TMR3H DATA 095H ; TIMER 3 HIGH BYTE
0098 +1 50 SCON0 DATA 098H ; SERIAL PORT 0 CONTROL
0099 +1 51 SBUF0 DATA 099H ; SERIAL PORT 0 BUFFER
009A +1 52 CPT1CN DATA 09AH ; COMPARATOR 1 CONTROL
009B +1 53 CPT0CN DATA 09BH ; COMPARATOR 0 CONTROL
009C +1 54 CPT1MD DATA 09CH ; COMPARATOR 1 MODE
009D +1 55 CPT0MD DATA 09DH ; COMPARATOR 0 MODE
009E +1 56 CPT1MX DATA 09EH ; COMPARATOR 1 MUX
009F +1 57 CPT0MX DATA 09FH ; COMPARATOR 0 MUX
00A0 +1 58 P2 DATA 0A0H ; PORT 2
A51 MACRO ASSEMBLER SPI_TEST_SAVE 04/26/2009 16:17:21 PAGE 2
00A1 +1 59 SPI0CFG DATA 0A1H ; SPI0 CONFIGURATION
00A2 +1 60 SPI0CKR DATA 0A2H ; SPI0 CLOCK CONFIGURATION
00A3 +1 61 SPI0DAT DATA 0A3H ; SPI0 DATA
00A4 +1 62 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE
00A5 +1 63 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE
00A6 +1 64 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE
00A7 +1 65 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE
00A8 +1 66 IE DATA 0A8H ; INTERRUPT ENABLE
00A9 +1 67 CLKSEL DATA 0A9H ; CLOCK SOURCE SELECT
00AA +1 68 EMI0CN DATA 0AAH ; EXTERNAL MEMORY INTERFACE CONTROL
00B0 +1 69 P3 DATA 0B0H ; PORT 3
00B1 +1 70 OSCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL
00B2 +1 71 OSCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL
00B3 +1 72 OSCICL DATA 0B3H ; INTERNAL OSCILLATOR CALIBRATION
00B5 +1 73 FLACL DATA 0B5H ; FLASH ACCESS LIMIT
00B6 +1 74 FLSCL DATA 0B6H ; FLASH SCALE
00B7 +1 75 FLKEY DATA 0B7H ; FLASH LOCK & KEY
00B8 +1 76 IP DATA 0B8H ; INTERRUPT PRIORITY
00BA +1 77 AMX0N DATA 0BAH ; ADC0 MUX NEGATIVE CHANNEL SELECTION
00BB +1 78 AMX0P DATA 0BBH ; ADC0 MUX POSITIVE CHANNEL SELECTION
00BC +1 79 ADC0CF DATA 0BCH ; ADC0 CONFIGURATION
00BD +1 80 ADC0L DATA 0BDH ; ADC0 DATA LOW
00BE +1 81 ADC0H DATA 0BEH ; ADC0 DATA HIGH
00C0 +1 82 SMB0CN DATA 0C0H ; SMBUS CONTROL
00C1 +1 83 SMB0CF DATA 0C1H ; SMBUS CONFIGURATION
00C2 +1 84 SMB0DAT DATA 0C2H ; SMBUS DATA
00C3 +1 85 ADC0GTL DATA 0C3H ; ADC0 GREATER-THAN LOW
00C4 +1 86 ADC0GTH DATA 0C4H ; ADC0 GREATER-THAN HIGH
00C5 +1 87 ADC0LTL DATA 0C5H ; ADC0 LESS-THAN LOW
00C6 +1 88 ADC0LTH DATA 0C6H ; ADC0 LESS-THAN HIGH
00C8 +1 89 TMR2CN DATA 0C8H ; TIMER 2 CONTROL
00CA +1 90 TMR2RLL DATA 0CAH ; TIMER 2 RELOAD LOW
00CB +1 91 TMR2RLH DATA 0CBH ; TIMER 2 RELOAD HIGH
00CC +1 92 TMR2L DATA 0CCH ; TIMER 2 LOW BYTE
00CD +1 93 TMR2H DATA 0CDH ; TIMER 2 HIGH BYTE
00D0 +1 94 PSW DATA 0D0H ; PROGRAM STATUS WORD
00D1 +1 95 REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL
00D4 +1 96 P0SKIP DATA 0D4H ; PORT 0 CROSSBAR SKIP
00D5 +1 97 P1SKIP DATA 0D5H ; PORT 1 CROSSBAR SKIP
00D6 +1 98 P2SKIP DATA 0D6H ; PORT 2 CROSSBAR SKIP
00D8 +1 99 PCA0CN DATA 0D8H ; PCA0 CONTROL
00D9 +1 100 PCA0MD DATA 0D9H ; PCA0 MODE
00DA +1 101 PCA0CPM0 DATA 0DAH ; PCA0 MODULE 0 MODE
00DB +1 102 PCA0CPM1 DATA 0DBH ; PCA0 MODULE 1 MODE
00DC +1 103 PCA0CPM2 DATA 0DCH ; PCA0 MODULE 2 MODE
00DD +1 104 PCA0CPM3 DATA 0DDH ; PCA0 MODULE 3 MODE
00DE +1 105 PCA0CPM4 DATA 0DEH ; PCA0 MODULE 4 MODE
00E0 +1 106 ACC DATA 0E0H ; ACCUMULATOR
00E1 +1 107 XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
00E2 +1 108 XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
00E4 +1 109 IT01CF DATA 0E4H ; INT0/INT1 CONFIGURATION
00E6 +1 110 EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1
00E8 +1 111 ADC0CN DATA 0E8H ; ADC 0 CONTROL
00E9 +1 112 PCA0CPL1 DATA 0E9H ; PCA0 MODULE 1 CAPTURE/COMPARE REGISTER LOW BYTE
00EA +1 113 PCA0CPH1 DATA 0EAH ; PCA0 MODULE 1 CAPTURE/COMPARE REGISTER HIGH BYTE
00EB +1 114 PCA0CPL2 DATA 0EBH ; PCA0 MODULE 2 CAPTURE/COMPARE REGISTER LOW BYTE
00EC +1 115 PCA0CPH2 DATA 0ECH ; PCA0 MODULE 2 CAPTURE/COMPARE REGISTER HIGH BYTE
00ED +1 116 PCA0CPL3 DATA 0EDH ; PCA0 MODULE 3 CAPTURE/COMPARE REGISTER LOW BYTE
00EE +1 117 PCA0CPH3 DATA 0EEH ; PCA0 MODULE 3 CAPTURE/COMPARE REGISTER HIGH BYTE
00EF +1 118 RSTSRC DATA 0EFH ; RESET SOURCE
00F0 +1 119 B DATA 0F0H ; B REGISTER
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