gmsk.tan.qmsg

为了满足对移动通信中带外的要求 GMSK调制器的改进 用数字信号处理方法实现Gmsk调制器

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk A4 clk_2 8.000 ns register " "Info: Minimum tco from clock \"clk\" to destination pin \"A4\" through register \"clk_2\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { clk } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clk_2 2 REG LC3 3 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 3; REG Node = 'clk_2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "0.000 ns" { clk clk_2 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk clk_2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clk_2 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_2 1 REG LC3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 3; REG Node = 'clk_2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { clk_2 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns A4 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'A4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "4.000 ns" { clk_2 A4 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 100.00 % ) " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "4.000 ns" { clk_2 A4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { clk_2 A4 } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk clk_2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clk_2 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "4.000 ns" { clk_2 A4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { clk_2 A4 } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "Minimum tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk A5 15.000 ns Shortest " "Info: Shortest tpd from source pin \"clk\" to destination pin \"A5\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { clk } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns clk~6 2 COMB LC19 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC19; Fanout = 1; COMB Node = 'clk~6'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "8.000 ns" { clk clk~6 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns A5 3 PIN PIN_21 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'A5'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "4.000 ns" { clk~6 A5 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns ( 93.33 % ) " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 6.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "15.000 ns" { clk clk~6 A5 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "15.000 ns" { clk clk~out clk~6 A5 } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 3.000ns 7.000ns 4.000ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 17 12:16:57 2009 " "Info: Processing ended: Tue Mar 17 12:16:57 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}