rominit.s

miceteck_MPC860_BSP源码,基于VXWORK

/* romInit.s - Motorola 860DAB ROM initialization module */

/* Copyright 1998 Teltec UCD-CS */
/* Copyright 1984-1996 Wind River Systems, Inc. */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01a,15sep98,rkh  started for DAB
01h,17dec96,tpr  fixed MAMR init. bug with 16 and 32 Mbytes dram (SPR #7661)
01g,10nov96,tpr  updated UPM table. 
		 removed RTCSC initialization.
01f,08nov96,tpr  modified UPM table for EDO Dram @ 50 Mhz.
01e,06nov96,tpr  replaced PLPRCR_MF_SFT by PLPRCR_MF_SHIFT.
01d,06nov96,tpr  Clean up the code (SPR #7336).
		 added DRAM speed selection (SPR #7335).
01c,24jun96,tpr  Reworked all initialization code.
01b,04jun96,cah  Add mem controller minimal init sequence
01a,19apr96,tpr  written.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"
	
	/* internals */

	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	.text
	.align 2

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:
	bl	cold		/* jump to the cold boot initialization */
	
	bl	start		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1996 Wind River Systems, Inc."
	.align 2

cold:
	li	r3, BOOT_COLD	/* set cold boot as start type */

	/*
	 * When the PowerPC 860 is powered on, the processor fletch the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */

	lis	r4, HIADJ(start)		/* load r4 with the address */
	addi	r4, r4, LO(start)		/* of start */

	lis	r5, HIADJ(romInit)		/* load r5 with the address */
	addi	r5, r5, LO(romInit)		/* of romInit() */

	lis	r6, HIADJ(ROM_TEXT_ADRS)	/* load r6 with the address */
	addi	r6, r6, LO(ROM_TEXT_ADRS)	/* of ROM_TEXT_ADRS */

	sub	r4, r4, r5			/*  */
	add	r4, r4, r6 

	mtspr	LR, r4				/* save destination address*/
						/* into LR register */
	blr					/* jump to flash mem address */
			
start:
	/* set the MSR register to a known state */

	xor	r4, r4, r4		/* clear register R4 */
	mtmsr 	r4			/* cleat the MSR register */

	/* DER - clear the Debug Enable Register */

	mtspr	DER, r4

	/* ICR - clear the Interrupt Cause Register */

	mtspr	ICR, r4

	/* 
	 * ICTRL - initialize the Intstruction Support Control register
	 *	   
	 */

	lis	r5, HIADJ(0x00000007)
	addi	r5, r5, LO(0x00000007)
	mtspr	ICTRL, r5

	/* disable the instruction/data cache */
	
	lis	r4, HIADJ ( CACHE_CMD_DISABLE)		/* load disable cmd */
	addi	r4, r4, LO (CACHE_CMD_DISABLE)
	mtspr	IC_CST, r4				/* disable I cache */
	mtspr	DC_CST, r4				/* disable D cache */

	/* unlock the instruction/data cache */

	lis	r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)	/* load unlock cmd */
	addi	r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
	mtspr	IC_CST, r4			/* unlock all I cache lines */
	mtspr	DC_CST, r4			/* unlock all D cache lines */

	/* invalidate the instruction/data cache */

	lis	r4, HIADJ ( CACHE_CMD_INVALIDATE)	/* load invalidate cmd*/
	addi	r4, r4, LO (CACHE_CMD_INVALIDATE)
	mtspr	IC_CST, r4		/* invalidate all I cache lines */
	mtspr	DC_CST, r4		/* invalidate all D cache lines */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification.
	 */

	lis	r4, HIADJ( INTERNAL_MEM_MAP_ADDR)	
	addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
	mtspr	IMMR, r4		/* initialize the IMMR register */

	mfspr	r4, IMMR		/* read it back, to be sure */
	rlwinm  r4, r4, 0, 0, 15	/* only high 16 bits count */

	/* SYPCR - turn off the system protection stuff */

	lis	r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	addi	r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	stw	r5, SYPCR(0)(r4)

	/* set the SIUMCR register for important debug port, etc... stuff */

	lwz	r5, SIUMCR(0)(r4)
	lis	r6, HIADJ( SIUMCR_FRC	       | SIUMCR_DLK  | SIUMCR_DPC | \
			   SIUMCR_MLRC_3STATES | SIUMCR_AEME | SIUMCR_GB5E)
	addi	r6, r6, LO(SIUMCR_FRC	       | SIUMCR_DLK  | SIUMCR_DPC | \
			   SIUMCR_MLRC_3STATES | SIUMCR_AEME | SIUMCR_GB5E)
	or	r5, r5, r6
	stw	r5, SIUMCR(0)(r4)

	/* TBSCR - initialize the Time Base Status and Control register */

	lis	r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
	addi	r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
	sth	r5, TBSCR(0)(r4)

	/* set PIT status and control init value */

	li	r5, PISCR_PS | PISCR_PITF
	sth	r5, PISCR(0)(r4)

	/* set the SPLL frequency to 50 Mhz : Mo */

	lis	r5, HIADJ( (SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \
								PLPRCR_TEXPS)
	addi	r5, r5, LO((SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \
								PLPRCR_TEXPS)
	stw	r5, PLPRCR(0)(r4)

	/* Power-up SDRAM initialisation */

	lis	r5, HIADJ( 0xfe000300)
	addi	r5, r5, LO(0xfe000300)
	stw	r5, OR5(0)(r4)

	lis	r5, HIADJ( 0x00000081)
	addi	r5, r5, LO( 0x00000081)
	stw	r5, BR5(0)(r4)

	lis	r5, HIADJ( 0x9c822111 )
	addi	r5, r5, LO(0x9c822111 )
	stw	r5, MAMR(0)(r4)

	li	r5, 0x0400
	sth	r5, MPTPR(0)(r4)

	li	r5, 0x0000
	sth	r5, MSTAT(0)(r4)

        /* Select the UPM power-up table for SDRAM */

	lis	r6, HIADJ( UpmPUTable)
	addi	r6, r6, LO(UpmPUTable)

	lis	r7, HIADJ( UpmPUTableEnd)
	addi	r7, r7, LO(UpmPUTableEnd)

	/* power-up init */

	sub	r5, r7, r6		/* compute table size */
	srawi	r5, r5, 2		/* in integer size */

	/* convert UpmPUTable to ROM based addressing */

	lis	r7, HIADJ(romInit)	
	addi	r7, r7, LO(romInit)

	lis	r8, HIADJ(ROM_TEXT_ADRS)
	addi	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7		/* subtract romInit base address */
	add	r6, r6, r8 		/* add in ROM_TEXT_ADRS address */

					/* Command: OP=Write, UPMA, MAD=0 */
	lis	r9, HIADJ ( 0x0 )
	addi	r9, r9, LO( 0x0 )

	addi	r9, r9, 8
	addi	r5, r5, 8

UpmPUWriteLoop:	
	/* write the UPM table in the UPM */

	lwz	r10, 0(r6)		/* get data from table */
	stw	r10, MDR(0)(r4)		/* store the data to MD register */

	stw	r9, MCR(0)(r4)		/* issue command to MCR register */

	addi	r6, r6, 4		/* next entry in the table */
	addi	r9, r9, 1		/* next MAD address */
	cmpw	r9, r5			/* done yet ? */
	blt	UpmPUWriteLoop

	/* Run Power-up sequence */

	lis	r5, HIADJ( 0xffffffff)
	addi	r5, r5, LO(0xffffffff )
	stw	r5, MDR(0)(r4)

	lis	r5, HIADJ( 0x02000088)
	addi	r5, r5, LO(0x02000088 )
	stw	r5, MAR(0)(r4)

	lis	r5, HIADJ( 0x8000aa08)
	addi	r5, r5, LO(0x8000aa08 )
	stw	r5, MCR(0)(r4)

        /* Select the UPM table for SDRAM */

	lis	r6, HIADJ( UpmTable)
	addi	r6, r6, LO(UpmTable)

	lis	r7, HIADJ( UpmTableEnd)
	addi	r7, r7, LO(UpmTableEnd)
	b	upmInit	

upmInit:
	/* init UPMA for memory access */

	sub	r5, r7, r6		/* compute table size */
	srawi	r5, r5, 2		/* in integer size */

	/* convert UpmTable to ROM based addressing */

	lis	r7, HIADJ(romInit)	
	addi	r7, r7, LO(romInit)

	lis	r8, HIADJ(ROM_TEXT_ADRS)
	addi	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7		/* subtract romInit base address */
	add	r6, r6, r8 		/* add in ROM_TEXT_ADRS address */

					/* Command: OP=Write, UPMA, MAD=0 */
	lis	r9, HIADJ ( 0x0 )
	addi	r9, r9, LO( 0x0 )

UpmWriteLoop:	
	/* write the UPM table in the UPM */

	lwz	r10, 0(r6)		/* get data from table */
	stw	r10, MDR(0)(r4)		/* store the data to MD register */

	stw	r9, MCR(0)(r4)		/* issue command to MCR register */

	addi	r6, r6, 4		/* next entry in the table */
	addi	r9, r9, 1		/* next MAD address */
	cmpw	r9, r5			/* done yet ? */
	blt	UpmWriteLoop

sdramInit:	
	/* Map the bank 5 to the SDram area */

 	lis	r5, HIADJ( 0xfe000300 )
	addi	r5, r5, LO( 0xfe000300 )
	stw	r5, OR5(0)(r4)	/* set OR5 to the previously computed value */

	lis	r5, HIADJ( 0x00000081 )
	addi	r5, r5, LO(0x00000081 )
	stw	r5, BR5(0)(r4)

	lis	r5, HIADJ( 0x9c822111 )
	addi	r5, r5, LO( 0x9c822111 )
	stw	r5, MAMR(0)(r4)

	/*
	 * Map the bank 0 to the flash area - On the 860pc board at reset time
	 * the bank 0 is already used to map the flash.
	 */
	lis	r5, HIADJ(0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, BR1(0)(r4)

	lis	r5, HIADJ(0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, OR1(0)(r4)

	lis	r5, HIADJ( 0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, BR2(0)(r4)

	lis	r5, HIADJ(0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, OR2(0)(r4)

/* Modified by Tang 2003-2-14 */ 	
/*
	lis	r5, HIADJ( 0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, BR3(0)(r4)

	lis	r5, HIADJ(0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, OR3(0)(r4)
*/

	lis	r5, HIADJ( 0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, BR4(0)(r4)

	lis	r5, HIADJ(0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, OR4(0)(r4)

	lis	r5, HIADJ( 0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, BR6(0)(r4)

	lis	r5, HIADJ(0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, OR6(0)(r4)

	lis	r5, HIADJ( 0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, BR7(0)(r4)

	lis	r5, HIADJ(0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, OR7(0)(r4)

	lis	r5, HIADJ( 0x02800401)
	addi	r5, r5, LO(0x02800401)
	stw	r5, BR0(0)(r4)

	lis	r5, HIADJ( 0xffe00920 )
	addi	r5, r5, LO(0xffe00920 )
	stw	r5, OR0(0)(r4)

/* Added by Tang 2003-2-14 */
/* Initialize Chip Select CS3, used for cpld registers */
/* CS3 Address Range: 3000.0000 - 3000.7FFF (32K)      */
        lis     r5,HI(0xFFFF8140)
        ori     r5,r5,LO(0xFFFF8140)
        stw     r5,OR3(0)(r4)              /* OR3 offset address:0x11C */

        lis     r5,HIADJ(0x30000401)
        ori     r5,r5,LO(0x30000401)
        stw     r5,BR3(0)(r4)              /* BR3 offset address:0x118 */
	
	
        /* initialize the stack pointer */

	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)
	
	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)		/* load R6 with C entry point */

	sub	r6, r6, r7			/* routine - entry point */
	add	r6, r6, r8 			/* + ROM base */

	mtlr	r6				/* move C entry point to LR */
	blr					/* jump to the C entry point */


UpmTable: 
   /* single read. (offset 0 in upm RAM) */
.long   0xfffffc04, 0x0f0cfc04, 0x0ffff804, 0x01bf7004
.long   0x0ffdd000, 0x1ffff447, 0x0ffffc04, 0x1ffffc07

   /* burst read. (offset 8 in upm RAM) */
.long   0xfffffc04, 0x0f0cfc04, 0x0ffff804, 0x00ff3004
.long   0x00fff000, 0x00fff000, 0x00fff000, 0x00fff000
.long   0x00fff000, 0x11fff447, 0xfffffc47, 0xfffffc04
.long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04

   /* single write. (offset 18 in upm RAM) */ 
.long   0xfffffc04, 0xfffffc04, 0x0f0cfc04, 0x0ffff800
.long   0x00af0004, 0x1ffdd447, 0xfffffc44, 0xfffffd47

   /* burst write. (offset 20 in upm RAM) */
.long   0xfffffc04, 0xfffffc04, 0x0f0cfc04, 0x0ffff800
.long   0x00ff0000, 0x00fff000, 0x00fff000, 0x00fff004
.long   0x11fff447, 0xfffffc47, 0xfffffc04, 0xfffffc04
.long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04

   /* refresh. (offset 30 in upm RAM) */
.long   0xeffeb804, 0x0ffc3004, 0xfffff004, 0xfffff004
.long   0xfffff447, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04

/* exception. (offset 3c in upm RAM) */
.long   0xffffec07, 0xffffffff, 0xffffffff, 0xffffffff

UpmTableEnd:

UpmPUTable:

.long   0xfffff004, 0x0ffcc004, 0xfffff004, 0xfffff034
.long   0x0fac0034, 0xfffff004, 0xfffff004, 0x0ffc3084
.long   0xfffff004, 0xfffff004, 0xfffff004, 0xfffff004
.long   0xfffff084, 0xfffff407

UpmPUTableEnd: