wddc_module.v

数字下变频的Verilog程序

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:55:39 04/23/07
// Design Name:     
// Module Name:    WDDC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
// To make full use of fc=fs/4 & HB filter ,here we do the polyphase decimator filter without IP core .
// we use only one HB filter to implement the IQ filter output and simplify the NCO and mixer of frequency.
//  --->     -->I---->>
//           -->Q---->>	the figure means the two branch of polyphase decimation filter do not add together but just 
//                      output their data seperately as output of the I way filtered data and Q way filtered data .
//                      By this idea, we carry out the IQ filter output just with one HB filter.
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments: 
// 
////////////////////////////////////////////////////////////////////////////////
module wddc_module(CLK, CE, AD_DIN, IQ_DOUT, DV );
//------------------Ports Declaration-------------------------------------------
	input 		    CLK;
	input 		    CE;
	input	  [13:0] AD_DIN;
	output  [31:0] IQ_DOUT;
   reg     [31:0] IQ_DOUT = 32'b0;	
	output          DV;
	
//	input           BF_CLK;
//	input  [12:2]   BF_ADDR;
//	input  [3:0]    WIQ_REN;
// output [15:0]   IQDtoPCI;//IQ data to PCI    
//	output          WIQ_INT;//Interrupt source register for WIQ.
//	output          WIQ_INTHF;//Interrupt source status register for WIQ
   
//-----------------Inner Signals Declaration -----------------------------------
	reg				[1:0]  stateflag = 2'b0;
	reg				[13:0] XIN = 0; 	
	reg 	signed  	[13:0] DX00 = 0;	//x(0)
	reg 	signed 	[13:0] DX02 = 0;
	reg 	signed  	[13:0] DX04 = 0;
	reg	signed	[13:0] DX06 = 0;
	reg	signed 	[13:0] DX08 = 0;
	reg 	signed	[13:0] DX10 = 0;
	reg	signed	[13:0] DX12 = 0;
	reg	signed	[13:0] DX14 = 0;
	reg	signed	[13:0] DX16 = 0;
	reg	signed	[13:0] DX18 = 0;
	reg	signed	[13:0] DX20 = 0;
	reg	signed	[13:0] DX22 = 0;
	reg	signed	[13:0] DX24 = 0;
	reg	signed	[13:0] DX26 = 0;
	reg	signed	[13:0] DX28 = 0;
	reg	signed	[13:0] DX30 = 0;
	reg	signed	[13:0] DX32 = 0;
	reg	signed	[13:0] DX34 = 0;
	reg	signed	[13:0] DX36 = 0;
	reg	signed	[13:0] DX38 = 0;
	reg	signed	[13:0] DX40 = 0;
	reg	signed	[13:0] DX42 = 0;
	reg	signed	[13:0] DX44 = 0;
	reg	signed	[13:0] DX46 = 0;
	reg	signed	[13:0] DX48 = 0;
	reg	signed	[13:0] DX50 = 0;	//x(50)
	reg     			[13:0] DX01 = 0;	//x(1)
	reg     			[13:0] DX03 = 0;
	reg     			[13:0] DX05 = 0;
	reg    			[13:0] DX07 = 0;
	reg    			[13:0] DX09 = 0;
	reg     			[13:0] DX11 = 0;
	reg     			[13:0] DX13 = 0;
	reg     			[13:0] DX15 = 0;
	reg     			[13:0] DX17 = 0;
	reg     			[13:0] DX19 = 0;
	reg     			[13:0] DX21 = 0;
	reg     			[13:0] DX23 = 0;
	reg     			[13:0] DX25 = 0;	//x(25)
	wire    			[15:0] A00;		//a(0) == a(50)
	wire    			[15:0] A02;		//a(2) == a(48)
	wire    			[15:0] A04;
	wire				[15:0] A06;
	wire				[15:0] A08;
	wire				[15:0] A10;
	wire				[15:0] A12;
	wire				[15:0] A14;
	wire				[15:0] A16;
	wire				[15:0] A18;
	wire				[15:0] A20;
	wire				[15:0] A22;
	wire				[15:0] A24;

	reg             State = 1'b0;
	reg	  [14:0] SUMA00,SUMA02,SUMA04,SUMA06,SUMA08,SUMA10,SUMA12,SUMA14,SUMA16,SUMA18,SUMA20,SUMA22,SUMA24;
	wire    [30:0] MULT00,MULT02,MULT04,MULT06,MULT08,MULT10,MULT12,MULT14,MULT16,MULT18,MULT20,MULT22,MULT24;
	reg	  [30:0] SUM_MULT_0,SUM_MULT_1,SUM_MULT_2,SUM_MULT_3,SUM_MULT_4,SUM_MULT_5;
	reg	  [30:0] SUM_MULT_A,SUM_MULT_B,SUM_MULT_C,SUM_MULT_X,SUM_MULT_Y;
	reg	  [30:0] MULT24_D1,MULT24_D2; 
	reg     [30:0] SUM = 0; //I way summary.	
	reg     [2:0]  flag = 3'b0;
	reg     [30:0] I_DOUT=0;
	reg     [15:0] Q_DOUT=0;
	
//=========================================================================

	always @(posedge CLK)	  //fnco/fs = 1/4
		begin
			if(CE)
				begin
					if(stateflag == 2'b00)
						begin
							XIN  <= AD_DIN;
							stateflag <= 2'b01;
						end
					else if(stateflag == 2'b01)
						begin
							XIN  <= ~AD_DIN + 1'b1;
							stateflag <= 2'b10;
						end
					else if(stateflag == 2'b10)
						begin			    
							XIN  <= ~AD_DIN + 1'b1;
							stateflag <= 2'b11;
						end
					else
						begin
							XIN  <= AD_DIN;
							stateflag <= 2'b00;
						end
				end
		end

//-------------------- polyphase decimator filter ----------------------------
	//Delay part
	always @(posedge CLK)
	   if(CE)
	      begin
		     if(State == 1'b0)
			    begin
					DX01   <= XIN;	//Delay Line
					DX03   <= DX01;
				   DX05   <= DX03;
					DX07   <= DX05; 
					DX09   <= DX07;
					DX11   <= DX09;
					DX13   <= DX11;	
					DX15   <= DX13;
					DX17   <= DX15;	
					DX19   <= DX17;	
					DX21   <= DX19;
					DX23   <= DX21;
					DX25   <= DX23;					        
					State <= 1'b1;
				end
			 else
			    begin
					DX00   <= XIN;
					DX02   <= DX00;
					DX04   <= DX02; 					
					DX06   <= DX04;
					DX08   <= DX06;
					DX10   <= DX08;
					DX12   <= DX10;
					DX14   <= DX12;
					DX16   <= DX14;
					DX18   <= DX16;
					DX20   <= DX18;
					DX22   <= DX20;
					DX24   <= DX22;
					DX26   <= DX24;
					DX28   <= DX26;					
					DX30   <= DX28;
					DX32   <= DX30;
					DX34   <= DX32;
					DX36   <= DX34;
					DX38   <= DX36;
					DX40   <= DX38;
					DX42   <= DX40;
					DX44   <= DX42;
					DX46   <= DX44;
					DX48   <= DX46;
					DX50   <= DX48;
					State <= 1'b0;	
					if(flag != 3'b110)
					   flag <= flag + 1'b1;
				end		    
		  end
	    else
		  begin
		     State <= 1'b0;
			  flag  <= 3'b0;
		  end

//----------------I way data output part ( NO.1 branch of polyphase decimation filter)--------------
	always @(posedge CLK)
		begin
			SUMA00 <= DX00 + DX50;	//DX00、DX02、……、DX50 need to be Set "reg signed [13:0]". 
			SUMA02 <= DX02 + DX48;
			SUMA04 <= DX04 + DX46;
			SUMA06 <= DX06 + DX44;
			SUMA08 <= DX08 + DX42;
			SUMA10 <= DX10 + DX40;
			SUMA12 <= DX12 + DX38;
			SUMA14 <= DX14 + DX36;
			SUMA16 <= DX16 + DX34;
			SUMA18 <= DX18 + DX32;
			SUMA20 <= DX20 + DX30;
			SUMA22 <= DX22 + DX28;	 
			SUMA24 <= DX24 + DX26;	//	
		end
	
	assign  A00 = 16'h0002;
	assign  A02 = 16'hfff8;
	assign  A04 = 16'h0014;
	assign  A06 = 16'hffd3;
	assign  A08 = 16'h0059;
	assign  A10 = 16'hff5f;
	assign  A12 = 16'h0112;
	assign  A14 = 16'hfe42;
	assign  A16 = 16'h02c0;
	assign  A18 = 16'hfbae;
	assign  A20 = 16'h0702;
	assign  A22 = 16'hf322;
	assign  A24 = 16'h2880;
	
	firmultiply modFIRMultiply0( 
			.CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA00), 
         .B_IN(A00),
			.P_OUT(MULT00) 
			); 

	firmultiply modFIRMultiply2( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA02), 
         .B_IN(A02),
			.P_OUT(MULT02) 
			); 

	firmultiply modFIRMultiply4( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA04), 
         .B_IN(A04),
			.P_OUT(MULT04) 
			); 
	
	firmultiply modFIRMultiply6( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA06), 
         .B_IN(A06),
			.P_OUT(MULT06) 
			);
	
	firmultiply modFIRMultiply8( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA08), 
         .B_IN(A08),
			.P_OUT(MULT08) 
			);

	firmultiply modFIRMultiply10( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA10), 
         .B_IN(A10),
			.P_OUT(MULT10) 
			);

	firmultiply modFIRMultiply12( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA12), 
         .B_IN(A12),
			.P_OUT(MULT12) );

	firmultiply modFIRMultiply14( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA14), 
         .B_IN(A14),
			.P_OUT(MULT14) 
			);
	
	firmultiply modFIRMultiply16( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA16), 
         .B_IN(A16),
			.P_OUT(MULT16) 
			);
	
	firmultiply modFIRMultiply18( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA18), 
         .B_IN(A18),
			.P_OUT(MULT18) 
			);

	firmultiply modFIRMultiply20( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA20), 
         .B_IN(A20),
			.P_OUT(MULT20) );

	firmultiply modFIRMultiply22( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA22), 
         .B_IN(A22),
			.P_OUT(MULT22) );

	firmultiply modFIRMultiply24( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN(SUMA24), 
         .B_IN(A24),
			.P_OUT(MULT24) 
			);
	
	always @(posedge CLK)						//加法树
		begin
			SUM_MULT_0 <= MULT00 + MULT02;
			SUM_MULT_1 <= MULT04 + MULT06;
			SUM_MULT_2 <= MULT08 + MULT10;
			SUM_MULT_3 <= MULT12 + MULT14;
			SUM_MULT_4 <= MULT16 + MULT18;
			SUM_MULT_5 <= MULT20 + MULT22;
			MULT24_D1  <= MULT24;
			SUM_MULT_A <= SUM_MULT_0 + SUM_MULT_1;
			SUM_MULT_B <= SUM_MULT_2 + SUM_MULT_3;
			SUM_MULT_C <= SUM_MULT_4 + SUM_MULT_5;
			MULT24_D2  <= MULT24_D1;
			SUM_MULT_X <= SUM_MULT_A + SUM_MULT_B;
			SUM_MULT_Y <= SUM_MULT_C + MULT24_D2;
			SUM		  <= SUM_MULT_X + SUM_MULT_Y;
		end

//-----------Q way data output part ( NO.2 branch of polyphase decimation filter) --------------------------------

	 //use shift operation instead of this multiplier  below
/*	
	assign  A25 = 16'h4000; 

	firmultiply modFIRMultiply4( 
	      .CLK_IN(CLK),
			.CE_IN(CE),
			.A_IN({{2{DX5[13]}},DX5[12:0]}), //symbol extend
         .B_IN(A25),
			.P_OUT(MULT5)); 

	 always @(posedge CLK)
		 if(CE)
			begin
			   MULT4D  <= MULT4;	  //need to be delayed 1 clock period
			   MULT5D1 <= MULT5;	  //need to be delayed 4 clock period
			   MULT5D2 <= MULT5D1;
			   MULT5D3 <= MULT5D2;
			   MULT5D  <= MULT5D3; 
			end
*/
	 //{{use shift operation  to get Q_DOUT from DX5 instead of	multiplier: modFIRMultiply4
	 reg    [30:0]  DX5E,DX5ES,Q_DX5ES1;
	 reg    [15:0]  Q_DX5ES,Q_DX5ES2,Q_DX5ES3,Q_DX5ES4,Q_DX5ES5,Q_DX5ES6;
	 
	 always@(posedge CLK)
	 	begin			//symbol extend to 32 bit to ensure the balance of Magnitude of I and Q way. 
			DX5E     <= {{18{DX25[13]}},DX25[12:0]};
			DX5ES    <= DX5E << 14;   //because A5 = 16'h4000
			Q_DX5ES1 <= DX5ES+{16'b0,~DX5ES[30],{13{DX5ES[30]}}};
			Q_DX5ES2 <= Q_DX5ES1[30:15];
			Q_DX5ES3 <= Q_DX5ES2;
			Q_DX5ES4 <= Q_DX5ES3;	
			Q_DX5ES5 <= Q_DX5ES4;
			Q_DX5ES6 <= Q_DX5ES5; 
			Q_DX5ES  <= Q_DX5ES6;	 
		end
	 //}}

//----------------------------- IQ filtered data output ---------------------------------------------
	 always @(posedge CLK) 
	 	begin
	 		I_DOUT <= SUM+{16'b0,~SUM[30],{13{SUM[30]}}}; 
	 		Q_DOUT <= Q_DX5ES;
		end
	 always @(posedge CLK) 
	 	begin
	  	   IQ_DOUT <= {Q_DOUT,I_DOUT[30:15]};	 
		end
      
		
	 assign DV = ((flag == 3'b110) ? ~State : 1'b0);  // data valid signal

//------------------- IQ Data Buffer --------------------------------------------------
   
//	//generate write address of DPRAM 
//	reg  [11:0] lADDRA_WDDC = 12'b0;
//	wire         lenal,lenah;
//	reg          lenal_d=0;
//	reg          lenah_d=0;
//	reg          lwiq_intl=0;
//	reg          lwiq_inth=0;
//	wire [15:0] lwi_lb,lwq_lb,lwi_hb,lwq_hb,lwiq_lb,lwiq_hb;
//	always @(posedge CLK)
//	   begin		  
//	      if(DV)
//		        lADDRA_WDDC <= lADDRA_WDDC + 1'b1;		  		  
//	   end
//   assign lenal = ~lADDRA_WDDC[11];
//	assign lenah =  lADDRA_WDDC[11];
//	//buffer IQ data to BF537,Low Block
//	dpram2k_ip modWI_LB (
//		.clka(CLK),
//		.addra(lADDRA_WDDC[10:0]),
//		.ena(lenal),				  	
//		.wea(DV),
//		.dina(IQ_DOUT[15:0]),
//		
//		.clkb(BF_CLK),
//		.addrb(BF_ADDR),	
//		.enb(WIQ_REN[0]),
//		.doutb(lwi_lb) 
//	 	);
//		
//   dpram2k_ip modWQ_LB (
//		.clka(CLK),
//		.addra(lADDRA_WDDC[10:0]),
//		.ena(lenal),				  	
//		.wea(DV),
//		.dina(IQ_DOUT[31:16]),
//		
//		.clkb(BF_CLK),
//		.addrb(BF_ADDR),	b
//		.enb(WIQ_REN[1]),
//		.doutb(lwq_lb) 
//	 	);
//		
//	//buffer IQ data to BF537,High Block
//	dpram2k_ip modWI_HB (
//		.clka(CLK),
//		.addra(lADDRA_WDDC[10:0]),
//		.ena(lenah),				  	
//		.wea(DV),
//		.dina(IQ_DOUT[15:0]),
//		
//		.clkb(BF_CLK),
//		.addrb(BF_ADDR),	
//		.enb(WIQ_REN[2]),
//		.doutb(lwi_hb) 
//	 	);
//		
//   dpram2k_ip modWQ_HB (
//		.clka(CLK),
//		.addra(lADDRA_WDDC[10:0]),
//		.ena(lenah),				  	
//		.wea(DV),
//		.dina(IQ_DOUT[31:16]),
//		
//		.clkb(BF_CLK),
//		.addrb(BF_ADDR),	
//		.enb(WIQ_REN[3]),
//		.doutb(lwq_hb) 
//	 	);
//   
//	always @(posedge CLK)
//	   begin
//		   lenal_d <= lenal;
//			lenah_d <= lenah;
//			lwiq_intl <= (lenal_d & lenah);
//			lwiq_inth <= (lenah_d & lenal);
//		end
//	
//	assign lwiq_lb = WIQ_REN[1] ? lwq_lb : lwi_lb;
//	assign lwiq_hb = WIQ_REN[3] ? lwq_hb : lwi_hb;
//	assign IQDtoPCI = (WIQ_REN[1]|WIQ_REN[0]) ? lwiq_lb : lwiq_hb;
//	
//	assign WIQ_INT = lwiq_intl|lwiq_inth;
//	assign WIQ_INTHF = lenal;//0-low block ready,1-high block ready.
 
endmodule