📄 mcc.h
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/****************************************************************************
* Property of Motorola, Wireless Infrastructure Systems Division
****************************************************************************
* ANSI C source code
*
* MCC Driver for WISD MSC8101 Driver Library
*
* MOTOROLA GENERAL BUSINESS INFORMATION
****************************************************************************/
/****************************************************************************
*
* MODULE: mcc.h
*
*****************************************************************************
* DESCRIPTION:MCC lib headers
*
* AUTHOR: Jim Gilbert.
*
* VERSION: v1.0, 20 Dec 2001.
*
* COMPILER: Metrowerks, CodeWarrior for Starcore Release 1.0
* IDE v4.1 Build 696.
*
* TARGET: StarCore/MSC8101 ADS.
*
* REVISION HISTORY: initial release v0.1, 01 Aug 2001.
* v1.0, 20 Dec 2001.
*****************************************************************************/
#ifndef _MCC_H
#define _MCC_H
/*****************************************************************************
* Defines
*****************************************************************************/
// If you change the payload of first data buffer transmitted in sync mode,
// you need to change the SYNC_MASK (MSB) from 0x11.
#define SYNC_MASK 0x11FF
// Maximum number of channels are allocated for data structures
// However there may be less active channels e.g physical TDM slots.
#define MCC1_NUM_CH 8 //active MCC1-channels (1...128)
#define MCC2_NUM_CH 8 //active MCC2-channels (1...128)
#define MCC1_NUM_CH_MAX 32 //total possible MCC1-channels (1...128)
#define MCC2_NUM_CH_MAX 32 //total possible MCC2-channels (1...128)
#define MCC_NUM_CH_MAX MCC1_NUM_CH_MAX //Maximum number of MCC channels
//which can be mapped to a scheduled channel
//i.e. largest of MCC1_NUM_CH_MAX and MCC2
#define TDMA1_SLOT_WIDTH 8 //should be 8 for this demo
#define TDMD2_SLOT_WIDTH 8 //should be 8 for this demo
#define MCC1_SI_ENTRIES 32 //SIRAM entries for active TDM = 32,64, or 128
#define MCC2_SI_ENTRIES 32
#define MCC1_TDM 0 //TDMA
#define MCC2_TDM 1 //1=TDMB, 2=TDMC, 3=TDMD
// Buffering Allowance parameters
#define FRAMES_NUM 3 //buffer space for 3 frames total per channel
#define MCC_MAX_NUM_BUF FRAMES_NUM*10 //allocation for MCC1_TxSubBufIrqIndex array entries
//Define number of buffers per BD-ring for MCC's Tx/Rx Channels.
#define MCC1_TX_NUM_BUF FRAMES_NUM //3
#define MCC1_RX_NUM_BUF FRAMES_NUM //3
#define MCC2_TX_NUM_BUF FRAMES_NUM //3
#define MCC2_RX_NUM_BUF FRAMES_NUM //3
//Define max. number of bytes per frame
#define MCC1_TX_BUF_SIZE 320
#define MCC1_RX_BUF_SIZE 320
#define MCC2_TX_BUF_SIZE 320
#define MCC2_RX_BUF_SIZE 320
//Define the base for the MCC1/MCC2 extra parameters. Here, the MCC2 extra
//parameters are put directly after the MCC1 extra parameter to save memory.
//Be aware that the value MCC2_XTRABASE-128*8 has to be written to the MCC2
//global parameter xtrabase because MCC2 is using the channels 128-255.
#define MCC1_XTRABASE 0xB000
#define MCC2_XTRABASE MCC1_XTRABASE + 8*MCC1_NUM_CH // 0xB100 for 32 ch
//Internal SRAM Base over local bus
#define LOCAL_BASE 0x02000000
//BD rings in LOCAL SRAM (Tx first, then Rx):
#define MCC1_BDRINGS_BASE 0x02051000
#define MCC1_BDRINGS_SIZE MCC1_NUM_CH*(MCC1_TX_NUM_BUF + MCC1_RX_NUM_BUF)*8
#define MCC2_BDRINGS_BASE MCC1_BDRINGS_BASE + MCC1_BDRINGS_SIZE
#define MCC2_BDRINGS_SIZE MCC2_NUM_CH*(MCC2_TX_NUM_BUF + MCC2_RX_NUM_BUF)*8
//Definition of interrupt circular tables! If you don't use some of the tables
//disable them by setting the appropriate _NUM to 0. (This will reduce code!)
#define MCC_INT_BASE 0x02050000
#define MCC1_TINT_BASE (MCC_INT_BASE+0x0200) //base of TINT interrupt circular table
#define MCC1_TINT_NUM 0x40 //number of TINT irq. circ. tab. entries
#define MCC1_RINT0_BASE (MCC_INT_BASE+0x0000) //base of RINT0 interrupt circular table
#define MCC1_RINT0_NUM 0x40 //number of RINT0 irq. circ. tab. entries
#define MCC1_RINT1_BASE 0x00000000 //base of RINT1 interrupt circular table
#define MCC1_RINT1_NUM 0 //number of RINT1 irq. circ. tab. entries
#define MCC1_RINT2_BASE 0x00000000 //base of RINT2 interrupt circular table
#define MCC1_RINT2_NUM 0 //number of RINT2 irq. circ. tab. entries
#define MCC1_RINT3_BASE 0x00000000 //base of RINT3 interrupt circular table
#define MCC1_RINT3_NUM 0 //number of RINT3 irq. circ. tab. entries
#define MCC2_TINT_BASE (MCC_INT_BASE+0x0300) //base of TINT interrupt circular table
#define MCC2_TINT_NUM 0x40 //number of TINT irq. circ. tab. entries
#define MCC2_RINT0_BASE (MCC_INT_BASE+0x0100) //base of RINT0 interrupt circular table
#define MCC2_RINT0_NUM 0x40 //number of RINT0 irq. circ. tab. entries
#define MCC2_RINT1_BASE 0x00000000 //base of RINT1 interrupt circular table
#define MCC2_RINT1_NUM 0 //number of RINT1 irq. circ. tab. entries
#define MCC2_RINT2_BASE 0x00000000 //base of RINT2 interrupt circular table
#define MCC2_RINT2_NUM 0 //number of RINT2 irq. circ. tab. entries
#define MCC2_RINT3_BASE 0x00000000 //base of RINT3 interrupt circular table
#define MCC2_RINT3_NUM 0 //number of RINT3 irq. circ. tab. entries
enum e_MCC_CP_CMD_OPCODE { TXRX_MCC, RX_MCC, TX_MCC };
/*****************************************************************************
* TypeDefs
*****************************************************************************/
typedef struct DrvBufs
{
UWord16 *pusiBufPtr; //ptr to buffer
UWord16 *pusiBufSize; //transfer length of buffer
UWord16 usiBufIrqFlag; //1=needing IRQ event.
} t_DrvBufs;
typedef struct Mcc1BD
{
UWord16 usiBdCstatus;
UWord16 usiBdLength; //transfer length
UWord32 uliBdAddr; //buffer address
} t_Mcc1BD;
typedef struct Mcc2BD
{
UWord16 usiBdCstatus;
UWord16 usiBdLength; //transfer length
UWord32 uliBdAddr; //buffer address
} t_Mcc2BD;
typedef struct Mcc1TxBDRing
{
t_Mcc1BD astBufD[MCC1_TX_NUM_BUF];
} t_Mcc1TxBDRing;
typedef struct Mcc1RxBDRing
{
t_Mcc1BD astBufD[MCC1_RX_NUM_BUF];
} t_Mcc1RxBDRing;
typedef struct Mcc2TxBDRing
{
t_Mcc2BD astBufD[MCC2_TX_NUM_BUF];
} t_Mcc2TxBDRing;
typedef struct Mcc2RxBDRing
{
t_Mcc2BD astBufD[MCC2_RX_NUM_BUF];
} t_Mcc2RxBDRing;
typedef struct Mcc1BDRings
{
t_Mcc1TxBDRing astTxChan[MCC1_NUM_CH];
t_Mcc1RxBDRing astRxChan[MCC1_NUM_CH];
} t_Mcc1BDRings;
typedef struct Mcc2BDRings
{
t_Mcc2TxBDRing astTxChan[MCC2_NUM_CH];
t_Mcc2RxBDRing astRxChan[MCC2_NUM_CH];
} t_Mcc2BDRings;
typedef struct SILast
{
UByte ucCmd; // command 1=open, 0=close
UByte ucChannum; // Mcc channel number
UByte ucBlocksize; // command line - logical channel param for open/close ch
} t_SILast;
/*****************************************************************************
* Function prototypes
*****************************************************************************/
void MCC1_InitParallelPorts(void);
void MCC1_InitGlobal (void);
void MCC1_InitSIRAM (void);
void MCC1_InitSpecific (UByte ucChanNum);
void MCC1_InitInterrupt(void);
void MCC1_InitTxChannel(UByte ucChanNum,
UWord32* puliTxBufPtr,
UWord16* pusiTxBufSize,
UByte* pucTxBufIrq,
UByte ucTxBufNum);
void MCC1_InitRxChannel(UByte ucChanNum,
UWord32* puliRxBufPtr,
UWord16* pusiRxBufSize,
UByte* pucRxBufIrq,
UByte ucRxBufNum);
void MCC1_StartChannel (UByte ucChanNum,
UByte ucBlockSize,
enum e_MCC_CP_CMD_OPCODE e_Opcode);
void MCC1_StopChannel (UByte ucChanNum,
UByte ucBlockSize,
enum e_MCC_CP_CMD_OPCODE e_Opcode);
void MCC2_InitParallelPorts(void);
void MCC2_InitGlobal (void);
void MCC2_InitSIRAM (void);
void MCC2_InitSpecific (UByte ucChanNum);
void MCC2_InitInterrupt(void);
void MCC2_InitTxChannel(UByte ucChanNum,
UWord32* puliTxBufPtr,
UWord16* pusiTxBufSize,
UByte* pucTxBufIrq,
UByte ucTxBufNum);
void MCC2_InitRxChannel(UByte ucChanNum,
UWord32* puliRxBufPtr,
UWord16* pusiRxBufSize,
UByte* pucRxBufIrq,
UByte ucRxBufNum);
void MCC2_StartChannel (UByte ucChanNum,
UByte ucBlockSize,
enum e_MCC_CP_CMD_OPCODE e_Opcode);
void MCC2_StopChannel (UByte ucChanNum,
UByte ucBlockSize,
enum e_MCC_CP_CMD_OPCODE e_Opcode);
#endif
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