📄 mcc.c
字号:
//channel number correct?
if (ChanNum<MCC1_NUM_CH)
{
pstMCCmch = (t_MChPRAM*)(IMM_BASE + (64 * ChanNum)); //offset 0x0000...0x1fff
}
else
{
asm(" debug");
}
memset(pstMCCmch,0,64); //clear 64 bytes (0x40) of channel-specific parameter RAM
//Channel-specific parameters:
pstMCCmch->vuliTState = 0x00000000; //reset
pstMCCmch->vuliZIState = 0x10000207; //regular channel
pstMCCmch->vuliZIData0 = 0xFFFFFFFF;
pstMCCmch->vuliZIData1 = 0xFFFFFFFF;
pstMCCmch->vusiTBDFlags = 0x0000;
pstMCCmch->vusiTBDCnt = 0x0000;
pstMCCmch->vuliTBDPtr = 0x00000000;
pstMCCmch->vusiIntMask = 0x0101; //enable TXB and RXB-interrupts
// pstMCCmch->vusiChaMR = 0x7400; //set MODE to TRAN, polling, reversed bit order, RINT0
pstMCCmch->vuliTCRC = 0x00000000;
pstMCCmch->vuliRState = 0x00000000; //reset
// pstMCCmch->vuliZDState = 0x50ffffe0; //changed for ucode patch for non-sync tran.
pstMCCmch->vuliZDData0 = 0xFFFFFFFF;
pstMCCmch->vuliZDData1 = 0xFFFFFFFF;
pstMCCmch->vusiRBDFlags = 0x0000;
pstMCCmch->vusiRBDCnt = 0x0000;
pstMCCmch->vuliRBDPtr = 0x00000000;
pstMCCmch->vusiMaxRLen = 0x0000;
// pstMCCmch->vusiSyncMaxCnt = 0x0000;
pstMCCmch->vuliRCRC = 0x00000000;
#if (MODE == HDLC)
/* HDLC */
{
/* HDLC Mode Settings */
pstMCCmch->vusiIntMask = 0x0105; //enable TXB, RXF and RXB-interrupts
pstMCCmch->vusiChaMR = 0xE080; //set MODE to HDLC,POL, RD, RINT0, SYNC 00
pstMCCmch->vuliZDState = 0x00FFFFE0; //changed for ucode patch for non-sync tran.
pstMCCmch->vusiSyncMaxCnt = 0x0000;
}
#elif (MODE == TRANS_SYNC)
{
/* Trasparent Mode Settings */
pstMCCmch->vusiIntMask = 0x0101; //enable TXB and RXB-interrupts
pstMCCmch->vusiChaMR = 0x7300; //set MODE to TRAN, POL, RD, RINT0, SYNC11 (16 Bit)
pstMCCmch->vuliZDState = 0x50ffffe0; //changed for ucode patch for non-sync tran.
pstMCCmch->vusiSyncMaxCnt = SYNC_MASK;
}
#elif (MODE == TRANS_NOSYNC)
{
/* Trasparent Mode Settings */
pstMCCmch->vusiIntMask = 0x0101; //enable TXB and RXB-interrupts
pstMCCmch->vusiChaMR = 0x7000; //set MODE to TRAN, POL, RD, RINT0, SYNC00
pstMCCmch->vuliZDState = 0x50ffffe0; //changed for ucode patch for non-sync tran.
pstMCCmch->vusiSyncMaxCnt = SYNC_MASK;
}
#else
#endif
//channel extra parameters:
pstMCCmchx = (t_MChXtraPRAM*)(IMM_BASE + MCC1_XTRABASE + (8 * ChanNum));
pstMCCmchx->vusiTBase = 0x0000;
pstMCCmchx->vusiTBPtr = 0x0000;
pstMCCmchx->vusiRBase = 0x0000;
pstMCCmchx->vusiRBPtr = 0x0000;
return;
}
/*****************************************************************************
* FUNCTION: MCC2_InitSpecific()
* PURPOSE: Configure MCC2 channel specific parameters
* NOTES: None.
* ENTRY: None
* EXIT: None.
*****************************************************************************/
void MCC2_InitSpecific(UByte ChanNum)
{
//establish pointer to multichannel params area and extra params area:
t_MChPRAM *pstMCCmch;
t_MChXtraPRAM *pstMCCmchx;
//convert to channel numbers 0...127, although the MCC2 normally uses the
//channels 128...255.
ChanNum &= 0x7F;
//channel number correct?
if (ChanNum<MCC2_NUM_CH)
{
pstMCCmch = (t_MChPRAM*)(IMM_BASE + 64*(ChanNum+128));//offset 0x2000...0x3fff
}
else
{
asm(" debug");
}
memset(pstMCCmch,0,64); //clear 64 bytes (0x40) of channel-specific parameter RAM
//Channel-specific parameters:
pstMCCmch->vuliTState = 0x00000000; //reset
pstMCCmch->vuliZIState = 0x10000207; //regular channel
pstMCCmch->vuliZIData0 = 0xFFFFFFFF;
pstMCCmch->vuliZIData1 = 0xFFFFFFFF;
pstMCCmch->vusiTBDFlags = 0x0000;
pstMCCmch->vusiTBDCnt = 0x0000;
pstMCCmch->vuliTBDPtr = 0x00000000;
pstMCCmch->vusiIntMask = 0x0101; //enable TXB and RXB-interrupts
// pstMCCmch->vusiChaMR = 0x7400; //set MODE to TRAN, polling, reversed bit order, RINT0
pstMCCmch->vuliTCRC = 0x00000000;
pstMCCmch->vuliRState = 0x00000000; //reset
// pstMCCmch->vuliZDState = 0x50ffffe0; //changed for ucode patch for non-sync tran.
pstMCCmch->vuliZDData0 = 0xFFFFFFFF;
pstMCCmch->vuliZDData1 = 0xFFFFFFFF;
pstMCCmch->vusiRBDFlags = 0x0000;
pstMCCmch->vusiRBDCnt = 0x0000;
pstMCCmch->vuliRBDPtr = 0x00000000;
pstMCCmch->vusiMaxRLen = 0x0000;
// pstMCCmch->vusiSyncMaxCnt = 0x0000;
pstMCCmch->vuliRCRC = 0x00000000;
#if (MODE == HDLC)
/* HDLC */
{
/* HDLC Mode Settings */
pstMCCmch->vusiIntMask = 0x0105; //enable TXB, RXF and RXB-interrupts
pstMCCmch->vusiChaMR = 0xE080; //set MODE to HDLC,POL, RD, RINT0, SYNC 00
pstMCCmch->vuliZDState = 0x00FFFFE0; //changed for ucode patch for non-sync tran.
pstMCCmch->vusiSyncMaxCnt = 0x0000;
}
#elif (MODE == TRANS_SYNC)
{
/* Trasparent Mode Settings */
pstMCCmch->vusiIntMask = 0x0101; //enable TXB and RXB-interrupts
pstMCCmch->vusiChaMR = 0x7300; //set MODE to TRAN, POL, RD, RINT0, SYNC11 (16 Bit)
pstMCCmch->vuliZDState = 0x50ffffe0; //changed for ucode patch for non-sync tran.
pstMCCmch->vusiSyncMaxCnt = SYNC_MASK;
}
#elif (MODE == TRANS_NOSYNC)
{
/* Trasparent Mode Settings */
pstMCCmch->vusiIntMask = 0x0101; //enable TXB and RXB-interrupts
pstMCCmch->vusiChaMR = 0x7000; //set MODE to TRAN, POL, RD, RINT0, SYNC00
pstMCCmch->vuliZDState = 0x50ffffe0; //changed for ucode patch for non-sync tran.
pstMCCmch->vusiSyncMaxCnt = SYNC_MASK;
}
#else
#endif
//channel extra parameters:
pstMCCmchx = (t_MChXtraPRAM*)(IMM_BASE + MCC2_XTRABASE + 8*ChanNum);
pstMCCmchx->vusiTBase = 0x0000;
pstMCCmchx->vusiTBPtr = 0x0000;
pstMCCmchx->vusiRBase = 0x0000;
pstMCCmchx->vusiRBPtr = 0x0000;
return;
}
/*****************************************************************************
* FUNCTION: MCC1_InitInterrupt()
* PURPOSE: Set up MCC1 Tx and Rx Interrupt Queues
* NOTES: None.
* ENTRY: None
* EXIT: None.
*****************************************************************************/
void MCC1_InitInterrupt(void)
{
UWord32 *puliMCCIrqCircTabBase;
t_8101IMM *pstIMM = (t_8101IMM*)IMM_BASE; //Pointer to internal memory*
pstIMM->t_aSIRegs[MCC1].vusiMCCE = 0xffff; //Clear MCCE reg. by writing all 1's
// IMM->t_aSIRegs[MCC1].mccm = 0x0000; //disable all MCC1 interrupts
pstIMM->t_aSIRegs[MCC1].vusiMCCM = 0x0003; //disable all MCC1 interrupts, except GUN & GOV
#if(MCC1_TINT_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC1_TINT_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC1_TINT_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC1_TINT_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC1].vusiMCCM |= 0x000C; //enable TINT related interrupts
#endif
#if(MCC1_RINT0_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC1_RINT0_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC1_RINT0_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC1_RINT0_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC1].vusiMCCM |= 0xC000; //enable RINT0 related interrupts
#endif
#if(MCC1_RINT1_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC1_RINT1_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC1_RINT1_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC1_RINT1_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC1].vusiMCCM |= 0x3000; //enable RINT1 related interrupts
#endif
#if(MCC1_RINT2_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC1_RINT2_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC1_RINT2_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC1_RINT2_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC1].vusiMCCM |= 0x0C00; //enable RINT2 related interrupts
#endif
#if(MCC1_RINT3_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC1_RINT3_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC1_RINT3_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC1_RINT3_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC1].vusiMCCM |= 0x0300; //enable RINT3 related interrupts
#endif
//Configure the SIU_CPM interrupt controller (SIC):
//When a MCC1 interrupt occurs, bit4 of the SIPNR_L will be set.
//Furthermore the corresponding interrupt code (MCC1=36) 0x90000000
//will be visible in SIVEC (dependent on priority level).
pstIMM->vuliICSIPnRL |= 0x08000000; //clear any previous MCC1 interrupt
pstIMM->vuliICSIMRL |= 0x08000000; //enable MCC1 interrupt
return;
}
/*****************************************************************************
* FUNCTION: MCC2_InitInterrupt()
* PURPOSE: Set up MCC2 Tx and Rx Interrupt Queues
* NOTES: None.
* ENTRY: None
* EXIT: None.
*****************************************************************************/
void MCC2_InitInterrupt(void)
{
UWord32 *puliMCCIrqCircTabBase;
t_8101IMM *pstIMM = (t_8101IMM*)IMM_BASE; //Pointer to internal memory*
pstIMM->t_aSIRegs[MCC2].vusiMCCE = 0xffff; //Clear MCCE reg. by writing all 1's
// pstIMM->si_regs[MCC2].vusiMCCM = 0x0000; //disable all MCC2 interrupts
pstIMM->t_aSIRegs[MCC2].vusiMCCM = 0x0003; //disable all MCC2 interrupts, except GUN & GOV
#if(MCC2_TINT_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC2_TINT_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC2_TINT_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC2_TINT_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC2].vusiMCCM |= 0x000C; //enable TINT related interrupts
#endif
#if(MCC2_RINT0_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC2_RINT0_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC2_RINT0_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC2_RINT0_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC2].vusiMCCM |= 0xC000; //enable RINT0 related interrupts
#endif
#if(MCC2_RINT1_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC2_RINT1_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC2_RINT1_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC2_RINT1_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC2].vusiMCCM |= 0x3000; //enable RINT1 related interrupts
#endif
#if(MCC2_RINT2_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC2_RINT2_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC2_RINT2_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC2_RINT2_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC2].vusiMCCM |= 0x0C00; //enable RINT2 related interrupts
#endif
#if(MCC2_RINT3_NUM>0)
puliMCCIrqCircTabBase = (UWord32*)MCC2_RINT3_BASE; //set pointer
memset(puliMCCIrqCircTabBase,0,MCC2_RINT3_NUM*4); //clear mem.(4 bytes/entry)
*(puliMCCIrqCircTabBase+MCC2_RINT3_NUM-1) = 0x40000000; //set wrap bit in last entry
pstIMM->t_aSIRegs[MCC2].vusiMCCM |= 0x0300; //enable RINT3 related interrupts
#endif
//Configure the SIU_CPM interrupt controller (SIC):
//When a MCC2 interrupt occurs, bit5 of the SIPNR_L will be set.
//Furthermore the corresponding interrupt code (MCC2=37) 0x94000000
//will be visible in SIVEC (dependent on priority level).
pstIMM->vuliICSIPnRL |= 0x04000000; //clear any previous MCC2 interrupt
pstIMM->vuliICSIMRL |= 0x04000000; //enable MCC2 interrupt
return;
}
/*****************************************************************************
* FUNCTION: MCC1_InitTxChannel()
* PURPOSE: Set up BD Ring for specific channel
* NOTES: None.
* ENTRY: None
* EXIT: None.
*****************************************************************************/
void MCC1_InitTxChannel(UByte ucChanNum,
UWord32* puliTxBufPtr,
UWord16* pusiTxBufSize,
UByte* pucTxBufIrq,
UByte ucTxBufNum
)
{
/* Memory is allocated in speech frames and then subblocks within
those frames are defined -> So memory blocks assumed contiguous.
For each buffer/sub-buffer a pointer must be provided within TxBufPtr.
ucChanNum - MCC channel number
puliTxBufPtr - Array of Frame/Subf buffer pointers. UWord32 TxBufPtr[TxBufNum]
pusiTxBufSize - Array of Frame/Subf sizes in bytes. UWord16 TxBufSize[TxBufNum]
pucTxBufIrq - Buffers which generate interrupts. UByte TxBufIrq[TxBufNum]
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -