mcc.c

ANSI C 源代码 WISD MSC8101的MCC驱动程序

/*****************************************************************************
* FUNCTION: MCC1_InitSIRAM()
* PURPOSE:  Configure MCC1 SIRAM - main and shadow
* NOTES:    None.
* ENTRY:    None
* EXIT:     None. 
*****************************************************************************/
void MCC1_InitSIRAM(void)
{
  /* 
    Initializes the serial interface RAM entry and registers
    Assumes only one TDM (TDMA) will be active for the SI  
 */
    
  UByte     ucCh; 
  UWord16   usiSI1Entry;
  t_8101IMM *pstIMM = (t_8101IMM*)IMM_BASE;  /*Pointer to internal memory*/ 
  
  /*
    programming the SIxRAM entries:
    
    bit00    : MCC functionality         = 1      => refer to MCC
    bit01    : channel loopback or echo  = 0/1    => echo mode for Tx only
    bit02    : super channel             = 0      => refer to regular channel
    bit03-10 : MCC channel select        = 'chan' => channel number
    bit11-13 : number of bits/bytes      = 001    => 2 bytes (or bits)
    bit14    : byte resolution           = 1      => byte reso. on
    bit15    : last entry of group       = 0/1    => 1 for last channel
  */
 
  //The 'TDMA1_SLOT_WIDTH' should be 1,2,3,...,8,16,24,...,64

 #if (TDMA1_SLOT_WIDTH < 8)
  usiSI1Entry = ((UWord16)(TDMA1_SLOT_WIDTH) - 1 ) << 2; //bit resolution
 #else
  usiSI1Entry = (((UWord16)(TDMA1_SLOT_WIDTH/8) - 1 ) << 2) | 0x0002; //byte resolution
 #endif

  memset((void *)pstIMM->t_aSIRAM[SI1].avusiTxSIRAM,0,512);
  memset((void *)pstIMM->t_aSIRAM[SI1].avusiRxSIRAM,0,512);

  for(ucCh=0;ucCh<MCC1_NUM_CH;ucCh++)
  {
    //original SIRAM:
    pstIMM->t_aSIRAM[SI1].avusiTxSIRAM[ucCh] = usiSI1Entry; 
    pstIMM->t_aSIRAM[SI1].avusiRxSIRAM[ucCh] = usiSI1Entry; 
    if(e_Loopback == LOOPBACK_SI)   // Set Loop bit in RX SIRAM
    { 
       pstIMM->t_aSIRAM[SI1].avusiRxSIRAM[ucCh] |= 0x4000; 
    } 
    
    //shadow SIRAM:
    pstIMM->t_aSIRAM[SI1].avusiTxSIRAM[MCC1_SI_ENTRIES+ucCh] = usiSI1Entry; 
    pstIMM->t_aSIRAM[SI1].avusiRxSIRAM[MCC1_SI_ENTRIES+ucCh] = usiSI1Entry; 
    if(e_Loopback == LOOPBACK_SI)   // Set Loop bit in RX SIRAM
    { 
       pstIMM->t_aSIRAM[SI1].avusiRxSIRAM[MCC1_SI_ENTRIES+ucCh] |= 0x4000; 
    }
    
  }
  //original SIRAM:
  pstIMM->t_aSIRAM[SI1].avusiTxSIRAM[MCC1_NUM_CH-1] |= 0x0001; // set last
  pstIMM->t_aSIRAM[SI1].avusiRxSIRAM[MCC1_NUM_CH-1] |= 0x0001;
  //shadow SIRAM:
  pstIMM->t_aSIRAM[SI1].avusiTxSIRAM[MCC1_SI_ENTRIES+MCC1_NUM_CH-1] |= 0x0001;
  pstIMM->t_aSIRAM[SI1].avusiRxSIRAM[MCC1_SI_ENTRIES+MCC1_NUM_CH-1] |= 0x0001;

  /*
    Set up the SI1 RAM Shadow Address Register (SI1RSR):

    bit00    : reserved                               = 0
    bit01-03 : Starting address SI-Shadow RAM (TDM_A) = 001 => first bank, 2nd 32 entries
    bit04    : reserved                               = 0
    bit05-07 : Starting address SI-Shadow RAM (TDM_B) = 000 => not used here
    bit08    : reserved                               = 0
    bit09-11 : Starting address SI-Shadow RAM (TDM_C) = 000 => not used here
    bit12    : reserved                               = 0
    bit13-15 : Starting address SI-Shadow RAM (TDM_D) = 000 => not used here
    
  */
  
  // Set First bank alternate 32 bytes 
  pstIMM->t_aSIRegs[SI1].vusiSIRSR = (MCC1_SI_ENTRIES/32) << ((3-MCC1_TDM)*4);


  /*
    Set up the CMX SI1 Clock Route Register:
    
    bit00    : receive TDM A1 clock source   = 0   => clk1
    bit01-03 : not used                      = 000
    bit04    : transmit TDM A1 clock source  = 0   => clk2
    bit05-07 : not used                      = 000
  */

#if (PHY == QUADFALC)  
    pstIMM->vucCMxSI1CR = 0x00;  //set CPM Mux Rx Clock to CLK1(TDMA1). Used for QuadFalc
#elif (PHY == NOPHY)
    pstIMM->vucCMxSI1CR = 0x00; // set CPM Mux Rx Clock to CLK1(TDMA1). Used for QuadFalc
#else
    {
       asm(" debug");
    }
#endif

  /* 
    Set up the SI mode register for TDM A to QUADFALC 2Mbps 
    
    bit00    : reserved                          = 0
    bit01-03 : starting bank address in memory   = 000 => 1.bank, 1st 32 entries
    bit04-05 : SI diagnostic mode                = 00  => normal operation
    bit06-07 : receive frame sync delay          = 00  => no bit delay
    bit08    : double speed clock                = 0   => chan. clock equal to data clock
    bit09    : Common receive and transmit pins  = 1   => common pins, same sync/clock pin
    bit10    : Sync level                        = 0   => sync. active on logic "1"
    bit11    : clock edge                        = 0   => data sent on rising edge
    bit12    : Frame sync edge                   = 1   => rising edge
    bit13    : Grant mode                        = 0   => GCI/SCIT mode
    bit14-15 : Transmit frame sync delay         = 00  => no bit delay
  */

  pstIMM->t_aSIRegs[SI1].avusiSIXR[MCC1_TDM] = 0x0000;   // Clear SIXMR

  if (e_Loopback == LOOPBACK_TDM)
  {
     pstIMM->t_aSIRegs[SI1].avusiSIXR[MCC1_TDM] |= 0x0800;
  }
  
  //Configure SI TDM mode/timing/loopback settings appropriately
  if (PHY == QUADFALC) 
  {
     pstIMM->t_aSIRegs[SI1].avusiSIXR[MCC1_TDM] |= 0x0048; // QuadFalc PHY loopback
  }
  else if (PHY == NO_PHY)
  {
     pstIMM->t_aSIRegs[SI1].avusiSIXR[MCC1_TDM] |= 0x0050; // NO PHY loopback
  }
  else
  {
     asm(" debug");  //Invalid PHY option
  }

  //Clear Last SIRAM operation storage
  stMcc1SILast.ucCmd      =0;
  stMcc1SILast.ucChannum  =0;
  stMcc1SILast.ucBlocksize=0;

  return;
} // end MCC1_InitSIRAM()


/*****************************************************************************
* FUNCTION: MCC2_InitSIRAM()
* PURPOSE:  Configure MCC2 SIRAM - main and shadow
* NOTES:    None.
* ENTRY:    None
* EXIT:     None. 
*****************************************************************************/
void MCC2_InitSIRAM(void)
{
  /* 
    Initializes the serial interface RAM entry and registers 
    Assumes only one TDM (TDMB, TDMC, TDMD) will be active for the SI  
  */
  

  UByte     ucCh; 
  UWord16   usiSI2Entry;
  t_8101IMM *pstIMM = (t_8101IMM*)IMM_BASE;  /*Pointer to internal memory*/ 
  /*
    programming the SIxRAM entries:
    
    bit00    : MCC functionality         = 1      => refer to MCC
    bit01    : channel loopback or echo  = 0/1    => echo mode for Tx only
    bit02    : super channel             = 0      => refer to regular channel
    bit03-10 : MCC channel select        = 'chan' => channel number
    bit11-13 : number of bits/bytes      = 001    => 2 bytes (or bits)
    bit14    : byte resolution           = 1      => byte reso. on
    bit15    : last entry of group       = 0/1    => 1 for last channel
  */
 
  //The 'TDMD2_SLOT_WIDTH' should be 1,2,3,...,8,16,24,...,64

 #if (TDMD2_SLOT_WIDTH < 8)
  usiSI2Entry = ((UWord16)(TDMD2_SLOT_WIDTH) - 1 ) << 2; //bit resolution
 #else
  usiSI2Entry = (((UWord16)(TDMD2_SLOT_WIDTH/8) - 1 ) << 2) | 0x0002; //byte resolution
 #endif

  memset((void *)pstIMM->t_aSIRAM[SI2].avusiTxSIRAM,0,512);
  memset((void *)pstIMM->t_aSIRAM[SI2].avusiRxSIRAM,0,512);

  for(ucCh=0; ucCh<MCC2_NUM_CH; ucCh++)
  {
    //original SIRAM:
    pstIMM->t_aSIRAM[SI2].avusiTxSIRAM[ucCh] = usiSI2Entry; 
    pstIMM->t_aSIRAM[SI2].avusiRxSIRAM[ucCh] = usiSI2Entry; 
    if(e_Loopback == LOOPBACK_SI)   // Set Loop bit in TX SIRAM
    { 
       pstIMM->t_aSIRAM[SI2].avusiRxSIRAM[ucCh] |= 0x4000; 
    } 

    //shadow SIRAM:
    pstIMM->t_aSIRAM[SI2].avusiTxSIRAM[MCC2_SI_ENTRIES+ucCh] = usiSI2Entry; 
    pstIMM->t_aSIRAM[SI2].avusiRxSIRAM[MCC2_SI_ENTRIES+ucCh] = usiSI2Entry; 
    if(e_Loopback == LOOPBACK_SI)   // Set Loop bit in TX SIRAM
    { 
       pstIMM->t_aSIRAM[SI2].avusiRxSIRAM[MCC2_SI_ENTRIES+ucCh] |= 0x4000; 
    }
    
    
  }
  //original SIRAM:
  pstIMM->t_aSIRAM[SI2].avusiTxSIRAM[MCC2_NUM_CH-1] |= 0x0001;  // set last
  pstIMM->t_aSIRAM[SI2].avusiRxSIRAM[MCC2_NUM_CH-1] |= 0x0001;
  //shadow SIRAM:
  pstIMM->t_aSIRAM[SI2].avusiTxSIRAM[MCC2_SI_ENTRIES+MCC2_NUM_CH-1] |= 0x0001;
  pstIMM->t_aSIRAM[SI2].avusiRxSIRAM[MCC2_SI_ENTRIES+MCC2_NUM_CH-1] |= 0x0001;

  /*
    Set up the SI2 RAM Shadow Address Register (SI2RSR):

    bit00    : reserved                               = 0
    bit01-03 : Starting address SI-Shadow RAM (TDM_A) = 000 => not used here
    bit04    : reserved                               = 0
    bit05-07 : Starting address SI-Shadow RAM (TDM_B) = 000 => not used here
    bit08    : reserved                               = 0
    bit09-11 : Starting address SI-Shadow RAM (TDM_C) = 000 => not used here
    bit12    : reserved                               = 0
    bit13-15 : Starting address SI-Shadow RAM (TDM_D) = 001 => first bank, 2nd 32 entries
    
  */
  
  // Set First bank alternate 32 bytes 
  pstIMM->t_aSIRegs[SI2].vusiSIRSR = (MCC2_SI_ENTRIES/32) << ((3-MCC2_TDM)*4); 


  /*
    Set up the CMX SI2 Clock Route Register:
    
    bit00    : not used                      = 0
    bit01    : receive TDM B2 clock source   = 0   => clk5
    bit02    : receive TDM C2 clock source   = 1   => clk7
    bit03    : receive TDM D2 clock source   = 1   => clk9
    bit04    : not used                      = 0
    bit05    : transmit TDM B2 clock source  = 0   => clk6
    bit06    : transmit TDM C2 clock source  = 0   => clk4
    bit07    : transmit TDM D2 clock source  = 0   => clk2
  */


#if (PHY == QUADFALC)  
    pstIMM->vucCMxSI1CR = 0x30;  //set CPM Mux Rx Clock to CLK5(TDMB2),CLK7(TDMC2),CLK9(TDMD2) Used for QuadFalc
#elif (PHY == NOPHY)
    pstIMM->vucCMxSI1CR = 0x30; // set CPM Mux Rx Clock to CLK5(TDMB2),CLK7(TDMC2),CLK9(TDMD2) Used for QuadFalc
#else
    {
       asm(" debug");
    }
#endif


  /* 
    Set up the SI mode register for TDM B to QUADFALC 2Mbps 
    
    bit00    : reserved                          = 0
    bit01-03 : starting bank address in memory   = 000 => 1.bank, 1st 32 entries
    bit04-05 : SI diagnostic mode                = 00  => normal operation
    bit06-07 : receive frame sync delay          = 00  => no bit delay
    bit08    : double speed clock                = 0   => chan. clock equal to data clock
    bit09    : Common receive and transmit pins  = 1   => common pins, same sync/clock pin
    bit10    : Sync level                        = 0   => sync. active on logic "1"
    bit11    : clock edge                        = 0   => data sent on rising edge
    bit12    : Frame sync edge                   = 1   => rising edge
    bit13    : Grant mode                        = 0   => GCI/SCIT mode
    bit14-15 : Transmit frame sync delay         = 00  => no bit delay
  */
  
  pstIMM->t_aSIRegs[SI2].avusiSIXR[MCC2_TDM] = 0x0000;   // Clear SIXMR

  if (e_Loopback == LOOPBACK_TDM)
  {
     pstIMM->t_aSIRegs[SI2].avusiSIXR[MCC2_TDM] |= 0x0800;
  }
  
  if (PHY == QUADFALC) 
  {
     pstIMM->t_aSIRegs[SI2].avusiSIXR[MCC2_TDM] |= 0x0048; // QuadFalc PHY loopback
  }
  else if (PHY == NO_PHY)
  {
     pstIMM->t_aSIRegs[SI2].avusiSIXR[MCC2_TDM] |= 0x0050; // NO PHY loopback
  }
  else
  {
     asm(" debug");  //Invalid PHY option
  }

  //Clear Last SIRAM operation storage
  stMcc1SILast.ucCmd      =0;
  stMcc1SILast.ucChannum  =0;
  stMcc1SILast.ucBlocksize=0;
    
  return;
} // end MCC2_InitSIRAM()


/*****************************************************************************
* FUNCTION: MCC1_InitSpecific()
* PURPOSE:  Configure MCC1 channel specific parameters
* NOTES:    None.
* ENTRY:    None
* EXIT:     None. 
*****************************************************************************/
void MCC1_InitSpecific(UByte ChanNum)
{
  //establish pointer to multichannel params area and extra params area:
  t_MChPRAM      *pstMCCmch;
  t_MChXtraPRAM  *pstMCCmchx;