📄 rc5decstmac.vhd
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-- Company:
-- Engineer: -- Create Date: 02/25/2009
-- Design Name:
-- Module Name: rc5decstmac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rc5decstmac is
port (
clr : IN STD_LOGIC; -- Asynchronous reset
clk : IN STD_LOGIC; -- Clock signal
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
di_vld: IN STD_LOGIC; -- input is valid
do_rdy: OUT STD_LOGIC); -- output is ready
end rc5decstmac;
architecture Behavioral of rc5decstmac is
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL a_sub : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_post: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL b_sub : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_post: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
-- define a type for round keys
TYPE rom IS ARRAY (0 TO 25) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
CONSTANT skey : rom:=rom'(X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5",X"460C6085",X"70F83B8A",X"284B8303",X"513E1454",X"F621ED22",X"3125065D",X"11A83A5D",X"D427686B",X"713AD82D",X"4B792F99",X"2799A4DD",X"A7901C49",X"DEDE871A",X"36C03196",X"A7EFC249",X"61A78BB8",X"3B0A1D2B",X"4DBFCA76",X"AE162167",X"30D76B0A",X"43192304",X"F6CC1431",X"65046380");
-- RC5 state machine has five states
TYPE StateType IS (ST_IDLE, --
ST_LOAD, -- intial load to register
ST_ROUND_OP, -- in this state RC5 round op is performed. The state machine remains in this state for twelve clock cycles.
ST_POST_ROUND, -- in this state RC5 post round operation is performed.
ST_READY --
);
-- RC5 state machine has five states: idle, pre_load, post_round, round and ready
SIGNAL state : StateType;
begin
--B=((B-S[2*i+1])>>> A) XOR A;
b_post<=b_reg - skey(1);
b_sub <=b_reg - skey(CONV_INTEGER(i_cnt & '1'));
with a_reg(4 downto 0)select
b_rot <= b_sub(0)& b_sub(31 downto 1)when "00001",
b_sub(1 downto 0)& b_sub(31 downto 2)when "00010",
b_sub(2 downto 0)& b_sub(31 downto 3)when "00011",
b_sub(3 downto 0)& b_sub(31 downto 4)when "00100",
b_sub(4 downto 0)& b_sub(31 downto 5)when "00101",
b_sub(5 downto 0)& b_sub(31 downto 6)when "00110",
b_sub(6 downto 0)& b_sub(31 downto 7)when "00111",
b_sub(7 downto 0)& b_sub(31 downto 8)when "01000",
b_sub(8 downto 0)& b_sub(31 downto 9)when "01001",
b_sub(9 downto 0)& b_sub(31 downto 10)when "01010",
b_sub(10 downto 0)& b_sub(31 downto 11)when "01011",
b_sub(11 downto 0)& b_sub(31 downto 12)when "01100",
b_sub(12 downto 0)& b_sub(31 downto 13)when "01101",
b_sub(13 downto 0)& b_sub(31 downto 14)when "01110",
b_sub(14 downto 0)& b_sub(31 downto 15)when "01111",
b_sub(15 downto 0)& b_sub(31 downto 16)when "10000",
b_sub(16 downto 0)& b_sub(31 downto 17)when "10001",
b_sub(17 downto 0)& b_sub(31 downto 18)when "10010",
b_sub(18 downto 0)& b_sub(31 downto 19)when "10011",
b_sub(19 downto 0)& b_sub(31 downto 20)when "10100",
b_sub(20 downto 0)& b_sub(31 downto 21)when "10101",
b_sub(21 downto 0)& b_sub(31 downto 22)when "10110",
b_sub(22 downto 0)& b_sub(31 downto 23)when "10111",
b_sub(23 downto 0)& b_sub(31 downto 24)when "11000",
b_sub(24 downto 0)& b_sub(31 downto 25)when "11001",
b_sub(25 downto 0)& b_sub(31 downto 26)when "11010",
b_sub(26 downto 0)& b_sub(31 downto 27)when "11011",
b_sub(27 downto 0)& b_sub(31 downto 28)when "11100",
b_sub(28 downto 0)& b_sub(31 downto 29)when "11101",
b_sub(29 downto 0)& b_sub(31 downto 30)when "11110",
b_sub(30 downto 0)& b_sub(31)when "11111",
b_sub when others;
b <= b_rot xor a_reg;
--A=((A*S[2*1])>>>B)xor B;
a_post<=a_reg - skey(0);
a_sub <= a_reg - skey(CONV_INTEGER(i_cnt&'0'));
with b(4 downto 0)select
a_rot <=
a_sub(0)& a_sub(31 downto 1)when "00001",
a_sub(1 downto 0)& a_sub(31 downto 2)when "00010",
a_sub(2 downto 0)& a_sub(31 downto 3)when "00011",
a_sub(3 downto 0)& a_sub(31 downto 4)when "00100",
a_sub(4 downto 0)& a_sub(31 downto 5)when "00101",
a_sub(5 downto 0)& a_sub(31 downto 6)when "00110",
a_sub(6 downto 0)& a_sub(31 downto 7)when "00111",
a_sub(7 downto 0)& a_sub(31 downto 8)when "01000",
a_sub(8 downto 0)& a_sub(31 downto 9)when "01001",
a_sub(9 downto 0)& a_sub(31 downto 10)when "01010",
a_sub(10 downto 0)& a_sub(31 downto 11)when "01011",
a_sub(11 downto 0)& a_sub(31 downto 12)when "01100",
a_sub(12 downto 0)& a_sub(31 downto 13)when "01101",
a_sub(13 downto 0)& a_sub(31 downto 14)when "01110",
a_sub(14 downto 0)& a_sub(31 downto 15)when "01111",
a_sub(15 downto 0)& a_sub(31 downto 16)when "10000",
a_sub(16 downto 0)& a_sub(31 downto 17)when "10001",
a_sub(17 downto 0)& a_sub(31 downto 18)when "10010",
a_sub(18 downto 0)& a_sub(31 downto 19)when "10011",
a_sub(19 downto 0)& a_sub(31 downto 20)when "10100",
a_sub(20 downto 0)& a_sub(31 downto 21)when "10101",
a_sub(21 downto 0)& a_sub(31 downto 22)when "10110",
a_sub(22 downto 0)& a_sub(31 downto 23)when "10111",
a_sub(23 downto 0)& a_sub(31 downto 24)when "11000",
a_sub(24 downto 0)& a_sub(31 downto 25)when "11001",
a_sub(25 downto 0)& a_sub(31 downto 26)when "11010",
a_sub(26 downto 0)& a_sub(31 downto 27)when "11011",
a_sub(27 downto 0)& a_sub(31 downto 28)when "11100",
a_sub(28 downto 0)& a_sub(31 downto 29)when "11101",
a_sub(29 downto 0)& a_sub(31 downto 30)when "11110",
a_sub(30 downto 0)& a_sub(31)when "11111",
a_sub when others;
a <= a_rot xor b;
-- A register
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
a_reg<=(OTHERS=>'0');
ELSIF(clk'EVENT AND clk='1') THEN
IF(state=ST_LOAD) THEN a_reg<=din(63 downto 32);
ELSIF(state=ST_ROUND_OP) THEN a_reg<=a;
ELSIF(state=ST_POST_ROUND) THEN a_reg<=a_post;
END IF;
END IF;
END PROCESS;
-- B register
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
b_reg<=(OTHERS=>'0');
ELSIF(clk'EVENT AND clk='1') THEN
IF(state=ST_LOAD) THEN b_reg<=din(31 downto 0);
ELSIF(state=ST_ROUND_OP) THEN b_reg<=b;
ELSIF(state=ST_POST_ROUND) THEN b_reg<=b_post;
END IF;
END IF;
END PROCESS;
PROCESS(clr, clk)
BEGIN
IF(clr='0') THEN
state<=ST_IDLE;
ELSIF(clk'EVENT AND clk='1') THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1') THEN state<=ST_LOAD; END IF;
WHEN ST_LOAD=> state<=ST_ROUND_OP;
WHEN ST_ROUND_OP=> IF(i_cnt="0001") THEN state<=ST_POST_ROUND; END IF;
WHEN ST_POST_ROUND=> state<=ST_READY;
WHEN ST_READY=> state<=ST_IDLE;
END CASE;
END IF;
END PROCESS;
-- round counter
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
i_cnt<="1100";
ELSIF(clk'EVENT AND clk='1') THEN
IF(state=ST_ROUND_OP) THEN
IF(i_cnt="0001") THEN i_cnt<="1100";
ELSE i_cnt<=i_cnt-'1';
END IF;
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<= '1' WHEN ST_READY,
'0' WHEN OTHERS;
end Behavioral;
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