controllor.txt

十字路口交通灯控制:分为主路和辅路

`timescale 1ns/100ps

`define s0=2'b00	//green,red
`define s1=2'b01	//yellow,red
`define s2=2'b11	//red,green
`define s3=2'b10	//red,yellow

module controllor(clk,reset,mgreen,myellow,mred,bgreen,byellow,bred);

input clk,reset;
output mgreen,myellow,mred,bgreen,byellow,bred;
reg mgreen,myellow,mred,bgreen,byellow,bred;
wire t1,t2,t3;		
reg st;                 // clear the count
reg [1:0] enable;
reg temp;
reg [1:0] currentstate;
reg [1:0] nextstate;
reg [3:0] time1,time2,time3;		//change time

always@(negedge clk or posedge reset)
   begin:count
	if(reset | st) 
	begin
		{time1,time2,time3}=12'b0;
		if(reset)
		begin
		enable=0;
		temp=0;
	
		end
	end
	else if((time1==9) & (time2==9) )
	begin
		time1=0;
		time2=0;
		time3=1;
	end
	else if((time1==9) & (time2!=9))
	begin
		time1=0;
		time2=time2+1;
	end
	else
	begin
		time1=time1+1;
	end
   end

assign t1=(time3==1) & (time2==4) & (time1==9);
assign t2=(time3==0) & (time2==0) & (time1==9);
assign t3=(time3==0) & (time2==6) & (time1==9);

always@(negedge clk or posedge reset)
   begin:statechange
	if(reset)
		currentstate <= 2'b00;
	else
		currentstate <= nextstate;
   end

always@(posedge clk)
   begin:fsm
	 case(currentstate)
	 	2'b00:begin
	 		nextstate=(t1)?2'b01:2'b00;
	 		st = (t1)?1:0;
	 	    end
		2'b01:begin
	 		nextstate=(t2)?2'b10:2'b01;
	 		st = (t2)?1:0;
	 	    end
	 	2'b10:begin
	 		nextstate=(t3)?2'b11:2'b10;
	 		st = (t3)?1:0;
	 	    end
	 	2'b11:begin
	 		nextstate=(t2)?2'b00:2'b11;
	 		st = (t2)?1:0;
	 	    end
	 endcase
   end
   
always@(currentstate)
   begin
   	case(currentstate)
   		2'b00:begin
   			{mgreen,myellow,mred}=3'b100;
   			{bgreen,byellow,bred}=3'b001;
   			enable=0;
   		    end
   		2'b01:begin
   			{mgreen,myellow,mred}=3'b010;
   			{bgreen,byellow,bred}=3'b001;
   			enable[0]=1;	
   		    end
   		2'b10:begin
   			{mgreen,myellow,mred}=3'b001;
   			{bgreen,byellow,bred}=3'b100;
   			enable=0;
   		    end
   		2'b11:begin
   			{mgreen,myellow,mred}=3'b001;
   			{bgreen,byellow,bred}=3'b010;
   			enable[1]=1;
   		    end
	endcase
   end
   
always@(negedge clk)
   begin
	if((enable[0]==1))
	begin
		myellow=temp;
	end
	if((enable[1]==1))
	begin
		byellow=temp;
	end
   end 

always@(posedge clk)
   begin
   if(time1[3])
   	temp=0;
   else
	temp=time1[0];
   end 
   
endmodule