c5416regs.h

ICETEK-VC5416-C使用说明书-audio

/*5416 CPU Memory-Mapped Registers*/
#define  IMR    *(int *)0x0000
#define  IFR    *(int *)0x0001
#define  ST0    *(int *)0x0006
#define  ST1    *(int *)0x0007
#define  AL     *(int *)0x0008
#define  AH     *(int *)0x0009
#define  AG     *(int *)0x000a
#define  BL     *(int *)0x000b
#define  BH     *(int *)0x000c
#define  BG     *(int *)0x000d
#define  T      *(int *)0x000e
#define  TRN    *(int *)0x000f
#define  AR0    *(int *)0x0010
#define  AR1    *(int *)0x0011
#define  AR2    *(int *)0x0012
#define  AR3    *(int *)0x0013
#define  AR4    *(int *)0x0014
#define  AR5    *(int *)0x0015
#define  AR6    *(int *)0x0016
#define  AR7    *(int *)0x0017
#define  SP     *(int *)0x0018
#define  BK     *(int *)0x0019
#define  BRC    *(int *)0x001a
#define  RSA    *(int *)0x001b
#define  REA    *(int *)0x001c
#define  PMST   *(int *)0x001d
#define  XPC    *(int *)0x001e
/*5416 On-chip Periperials Memory-Mapped Register*/
#define  DRR20   *(int *)0x20 /*McBSP 0 Data Receive Register 2                           */
#define  DRR10   *(int *)0x21 /*McBSP 0 Data Receive Register 1                           */
#define  DXR20   *(int *)0x22 /*McBSP 0 Data Transmit Register 2                          */
#define  DXR10   *(int *)0x23 /*McBSP 0 Data Transmit Register 1                          */
#define  TIM     *(int *)0x24 /*Timer Register                                            */
#define  PRD     *(int *)0x25 /*Timer Period Register                                     */
#define  TCR     *(int *)0x26 /*Timer Control Register                                    */
#define  SWWSR   *(int *)0x28 /*Software Wait-State Register                              */
#define  BSCR    *(int *)0x29 /*Bank-Switching Control Register                           */
#define  SWCR    *(int *)0x2B /*Software Wait-State Control Register                      */
#define  HPIC    *(int *)0x2C /*HPI Control Register (HMODE = 0 only)                     */
#define  DRR22   *(int *)0x30 /*McBSP 2 Data Receive Register 2                           */
#define  DRR12   *(int *)0x31 /*McBSP 2 Data Receive Register 1                           */
#define  DXR22   *(int *)0x32 /*McBSP 2 Data Transmit Register 2                          */
#define  DXR12   *(int *)0x33 /*McBSP 2 Data Transmit Register 1                          */
#define  SPSA2   *(int *)0x34 /*McBSP 2 Subbank Address Register