📄 hdb3.map.rpt
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; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 30 ;
; -- arithmetic mode ; 31 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 32 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 48 ;
; Total logic cells in carry chains ; 32 ;
; I/O pins ; 5 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 48 ;
; Total fan-out ; 238 ;
; Average fan-out ; 3.61 ;
+---------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |HDB3 ; 61 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 ; 0 ; 13 (0) ; 6 (0) ; 42 (0) ; 32 (0) ; 0 (0) ; |HDB3 ;
; |codeout:inst2| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |HDB3|codeout:inst2 ;
; |insertb:inst1| ; 13 (13) ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 (0) ; |HDB3|insertb:inst1 ;
; |insertv:inst| ; 45 (45) ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 34 (34) ; 32 (32) ; 0 (0) ; |HDB3|insertv:inst ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 48 ;
; Number of registers using Synchronous Clear ; 32 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 4 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |HDB3|insertv:inst|codeoutv[1] ;
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |HDB3|codeout:inst2|code[1] ;
; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |HDB3|insertv:inst|count0[29] ;
; 7:1 ; 2 bits ; 8 LEs ; 2 LEs ; 6 LEs ; Yes ; |HDB3|insertb:inst1|codeoutb[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+-----------------------------------------+
; Source assignments for insertb:inst1 ;
+----------------+-------+------+---------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+---------+
; POWER_UP_LEVEL ; Low ; - ; flag1 ;
; POWER_UP_LEVEL ; Low ; - ; count1 ;
; POWER_UP_LEVEL ; Low ; - ; firstv ;
; POWER_UP_LEVEL ; Low ; - ; reg1[0] ;
; POWER_UP_LEVEL ; Low ; - ; reg1[1] ;
; POWER_UP_LEVEL ; Low ; - ; reg1[2] ;
; POWER_UP_LEVEL ; Low ; - ; reg0[0] ;
; POWER_UP_LEVEL ; Low ; - ; reg0[1] ;
; POWER_UP_LEVEL ; Low ; - ; reg0[2] ;
+----------------+-------+------+---------+
+--------------------------------------------+
; Source assignments for insertv:inst ;
+----------------+-------+------+------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+------------+
; POWER_UP_LEVEL ; Low ; - ; count0[0] ;
; POWER_UP_LEVEL ; Low ; - ; count0[1] ;
; POWER_UP_LEVEL ; Low ; - ; count0[2] ;
; POWER_UP_LEVEL ; Low ; - ; count0[3] ;
; POWER_UP_LEVEL ; Low ; - ; count0[4] ;
; POWER_UP_LEVEL ; Low ; - ; count0[5] ;
; POWER_UP_LEVEL ; Low ; - ; count0[6] ;
; POWER_UP_LEVEL ; Low ; - ; count0[7] ;
; POWER_UP_LEVEL ; Low ; - ; count0[8] ;
; POWER_UP_LEVEL ; Low ; - ; count0[9] ;
; POWER_UP_LEVEL ; Low ; - ; count0[10] ;
; POWER_UP_LEVEL ; Low ; - ; count0[11] ;
; POWER_UP_LEVEL ; Low ; - ; count0[12] ;
; POWER_UP_LEVEL ; Low ; - ; count0[13] ;
; POWER_UP_LEVEL ; Low ; - ; count0[14] ;
; POWER_UP_LEVEL ; Low ; - ; count0[15] ;
; POWER_UP_LEVEL ; Low ; - ; count0[16] ;
; POWER_UP_LEVEL ; Low ; - ; count0[17] ;
; POWER_UP_LEVEL ; Low ; - ; count0[18] ;
; POWER_UP_LEVEL ; Low ; - ; count0[19] ;
; POWER_UP_LEVEL ; Low ; - ; count0[20] ;
; POWER_UP_LEVEL ; Low ; - ; count0[21] ;
; POWER_UP_LEVEL ; Low ; - ; count0[22] ;
; POWER_UP_LEVEL ; Low ; - ; count0[23] ;
; POWER_UP_LEVEL ; Low ; - ; count0[24] ;
; POWER_UP_LEVEL ; Low ; - ; count0[25] ;
; POWER_UP_LEVEL ; Low ; - ; count0[26] ;
; POWER_UP_LEVEL ; Low ; - ; count0[27] ;
; POWER_UP_LEVEL ; Low ; - ; count0[28] ;
; POWER_UP_LEVEL ; Low ; - ; count0[29] ;
; POWER_UP_LEVEL ; Low ; - ; count0[30] ;
; POWER_UP_LEVEL ; Low ; - ; count0[31] ;
+----------------+-------+------+------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
Info: Processing started: Thu Apr 02 18:43:19 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off HDB3 -c HDB3
Info: Found 1 design units, including 1 entities, in source file HDB3.bdf
Info: Found entity 1: HDB3
Info: Elaborating entity "HDB3" for the top level hierarchy
Warning: Using design file codeout.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: codeout-one
Info: Found entity 1: codeout
Info: Elaborating entity "codeout" for hierarchy "codeout:inst2"
Warning: Using design file insertb.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: insertb-one
Info: Found entity 1: insertb
Info: Elaborating entity "insertb" for hierarchy "insertb:inst1"
Warning: Using design file insertv.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: insertv-one
Info: Found entity 1: insertv
Info: Elaborating entity "insertv" for hierarchy "insertv:inst"
Info: Implemented 66 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 2 output pins
Info: Implemented 61 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Processing ended: Thu Apr 02 18:43:21 2009
Info: Elapsed time: 00:00:02
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