hdb3.map.qmsg

实现HDB3编码,使用VHDL语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 02 18:43:19 2009 " "Info: Processing started: Thu Apr 02 18:43:19 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off HDB3 -c HDB3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off HDB3 -c HDB3" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "HDB3.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file HDB3.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 HDB3 " "Info: Found entity 1: HDB3" {  } { { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "HDB3 " "Info: Elaborating entity \"HDB3\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "codeout.vhd 2 1 " "Warning: Using design file codeout.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 codeout-one " "Info: Found design unit 1: codeout-one" {  } { { "codeout.vhd" "" { Text "E:/Quartus II/HDB3/codeout.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 codeout " "Info: Found entity 1: codeout" {  } { { "codeout.vhd" "" { Text "E:/Quartus II/HDB3/codeout.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "codeout codeout:inst2 " "Info: Elaborating entity \"codeout\" for hierarchy \"codeout:inst2\"" {  } { { "HDB3.bdf" "inst2" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 152 640 816 248 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "insertb.vhd 2 1 " "Warning: Using design file insertb.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 insertb-one " "Info: Found design unit 1: insertb-one" {  } { { "insertb.vhd" "" { Text "E:/Quartus II/HDB3/insertb.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 insertb " "Info: Found entity 1: insertb" {  } { { "insertb.vhd" "" { Text "E:/Quartus II/HDB3/insertb.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "insertb insertb:inst1 " "Info: Elaborating entity \"insertb\" for hierarchy \"insertb:inst1\"" {  } { { "HDB3.bdf" "inst1" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 168 424 616 264 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "insertv.vhd 2 1 " "Warning: Using design file insertv.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 insertv-one " "Info: Found design unit 1: insertv-one" {  } { { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 insertv " "Info: Found entity 1: insertv" {  } { { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "insertv insertv:inst " "Info: Elaborating entity \"insertv\" for hierarchy \"insertv:inst\"" {  } { { "HDB3.bdf" "inst" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 184 232 392 280 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "66 " "Info: Implemented 66 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "61 " "Info: Implemented 61 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 02 18:43:21 2009 " "Info: Processing ended: Thu Apr 02 18:43:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}