hdb3.sim.rpt

来自「实现HDB3编码,使用VHDL语言」· RPT 代码 · 共 410 行 · 第 1/5 页

; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|result_node[0]            ; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|result_node[0]                 ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|_~4                       ; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|_~4                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|_~5                       ; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|_~5                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|_~6                       ; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|_~6                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|w_result19w~0             ; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|w_result19w~0                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|_~7                       ; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|_~7                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|w_result19w~1             ; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|w_result19w~1                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|w_result19w               ; |HDB3|insertb:inst1|lpm_mux:Mux4|mux_gdc:auto_generated|w_result19w                    ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~0                       ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~0                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~1                       ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~1                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|result_node[0]~0          ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|result_node[0]~0               ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~2                       ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~2                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~3                       ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~3                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|result_node[0]~1          ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|result_node[0]~1               ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|result_node[0]            ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|result_node[0]                 ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~4                       ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~4                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~5                       ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~5                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~6                       ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~6                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|w_result19w~0             ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|w_result19w~0                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~7                       ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|_~7                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|w_result19w~1             ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|w_result19w~1                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|w_result19w               ; |HDB3|insertb:inst1|lpm_mux:Mux3|mux_gdc:auto_generated|w_result19w                    ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~0                       ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~0                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~1                       ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~1                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|result_node[0]~0          ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|result_node[0]~0               ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~2                       ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~2                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~3                       ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~3                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|result_node[0]~1          ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|result_node[0]~1               ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|result_node[0]            ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|result_node[0]                 ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~4                       ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~4                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~5                       ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~5                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~6                       ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~6                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|w_result19w~0             ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|w_result19w~0                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~7                       ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|_~7                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|w_result19w~1             ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|w_result19w~1                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|w_result19w               ; |HDB3|insertb:inst1|lpm_mux:Mux2|mux_gdc:auto_generated|w_result19w                    ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~0                       ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~0                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~1                       ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~1                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|result_node[0]~0          ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|result_node[0]~0               ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~2                       ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~2                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~3                       ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~3                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|result_node[0]~1          ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|result_node[0]~1               ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|result_node[0]            ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|result_node[0]                 ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~4                       ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~4                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~5                       ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~5                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~6                       ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~6                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|w_result19w~0             ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|w_result19w~0                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~7                       ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|_~7                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|w_result19w~1             ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|w_result19w~1                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|w_result19w               ; |HDB3|insertb:inst1|lpm_mux:Mux1|mux_gdc:auto_generated|w_result19w                    ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~0                       ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~0                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~1                       ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~1                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|result_node[0]~0          ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|result_node[0]~0               ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~2                       ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~2                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|result_node[0]~1          ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|result_node[0]~1               ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|result_node[0]            ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|result_node[0]                 ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~4                       ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~4                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~5                       ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~5                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~6                       ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|_~6                            ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|w_result19w~0             ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|w_result19w~0                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|w_result19w~1             ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|w_result19w~1                  ; out0             ;
; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|w_result19w               ; |HDB3|insertb:inst1|lpm_mux:Mux0|mux_gdc:auto_generated|w_result19w                    ; out0             ;
; |HDB3|insertb:inst1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0            ; |HDB3|insertb:inst1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                 ; out0             ;
; |HDB3|insertb:inst1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]              ; |HDB3|insertb:inst1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                   ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|result_node[0]                                ; |HDB3|insertv:inst|lpm_add_sub:Add0|result_node[0]                                     ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|result_node[1]                                ; |HDB3|insertv:inst|lpm_add_sub:Add0|result_node[1]                                     ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|result_node[2]                                ; |HDB3|insertv:inst|lpm_add_sub:Add0|result_node[2]                                     ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0             ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                  ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]               ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                    ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~0                             ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~0                                  ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~3                             ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~3                                  ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~31            ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~31                 ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]               ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]               ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~65                            ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~65                                 ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~96                            ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~96                                 ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~127                           ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|_~127                                ; out0             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |HDB3|insertv:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;