ve100.h

Linux 下的ve100网卡驱动

/* 
	device driver for network card
	Intel pro/100 VE 82801db
	written by Team X
	2008-5
*/
#ifndef _VE100_H_
#define _VE100_H_

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/if_vlan.h>
#include <linux/skbuff.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/string.h>
#include <asm/unaligned.h>

#define DRV_NAME	"ve100"
#define DRV_EXT		"-NAPI"
#define DRV_VERSION "3.5.16-k2"DRV_EXT
#define DRV_DESCRIPTION	"Intel pro/100 ve 82801db"
#define DRV_COPYRIGHT		"Copyright(c) 1999-2006 Intel Corporation"
#define	PFX		DRV_NAME	": "

#define VE100_WATCHDOG_PERIOD	(2*HZ)
#define	VE100_NAPI_WEIGHT	16

MODULE_AUTHOR(DRV_COPYRIGHT);
MODULE_DESCRIPTION(DRV_DESCRIPTION);
MODULE_VERSION(DRV_VERSION);
MODULE_LICENSE("GPL");

static int debug = 3;
static int eeprom_bad_csum_allow = 0;
static int use_io = 0;
module_param(eeprom_bad_csum_allow,int,0);
module_param(debug,int,0);
MODULE_PARM_DESC(debug,"Debug level 0-16");
MODULE_PARM_DESC(eeprom_bad_csum_allow,"bad csum allow");
MODULE_PARM_DESC(use_io, "Force use of i/o access mode");

#define INTEL_8255X_ETHERNET_DEVICE(device_id,ich) {\
		PCI_VENDOR_ID_INTEL,device_id,PCI_ANY_ID,PCI_ANY_ID,	\
	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
static struct pci_device_id ve100_id_tbl[] = {
	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
	INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
	INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
	INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
	INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
	INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
	{ 0, }
};
MODULE_DEVICE_TABLE(pci,ve100_id_tbl);

enum mac {
	mac_82557_D100_A  = 0,
	mac_82557_D100_B  = 1,
	mac_82557_D100_C  = 2,
	mac_82558_D101_A4 = 4,
	mac_82558_D101_B0 = 5,
	mac_82559_D101M   = 8,
	mac_82559_D101S   = 9,
	mac_82550_D102    = 12,
	mac_82550_D102_C  = 13,
	mac_82551_E       = 14,
	mac_82551_F       = 15,
	mac_82551_10      = 16,
	mac_unknown       = 0xFF,
};

enum phy {
	phy_100a     = 0x000003E0,
	phy_100c     = 0x035002A8,
	phy_82555_tx = 0x015002A8,
	phy_nsc_tx   = 0x5C002000,
	phy_82562_et = 0x033002A8,
	phy_82562_em = 0x032002A8,
	phy_82562_ek = 0x031002A8,
	phy_82562_eh = 0x017002A8,
	phy_unknown  = 0xFFFFFFFF,
};

/* control and status registers */
struct csr 
{
		struct 
		{
			u8 status;
			u8 stat_ack;
			u8 cmd_low;
			u8 cmd_high;
			u32 gen_ptr;
		}	scb;
		u32 port;
		u16 flash_ctrl;
		u8	eeprom_ctrl_low;
		u8 	eeprom_ctrl_high;
		u32 mdi_ctrl;
		u32 rx_dma_count;
};

enum scb_status
{
		rus_ready = 0x10,
		rus_mask	= 0x3C,
};
/* receive units state */
enum ru_state
{
		RU_SUSPENDED = 0,
		RU_RUNNING = 1,
		RU_UNINITIALIZED = -1,
};

/* system control block state acknowledge */
enum scb_stat_ack
{
	stat_ack_not_ours    = 0x00,
	stat_ack_sw_gen      = 0x04,
	stat_ack_rnr         = 0x10,
	stat_ack_cu_idle     = 0x20,
	stat_ack_frame_rx    = 0x40,
	stat_ack_cu_cmd_done = 0x80,
	stat_ack_not_present = 0xFF,
	stat_ack_rx = ( stat_ack_rnr | stat_ack_frame_rx | stat_ack_sw_gen),
	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
};

/* system control block command high bits */
enum scb_cmd_high
{
	irq_mask_none = 0x00,
	irq_mask_all = 0x01,
	irq_sw_gen = 0x02,
};

/* system control block command low bits */
enum scb_cmd_low
{
	cuc_nop = 0x00,
	ruc_start = 0x01,
	ruc_load_base = 0x06,
	cuc_start = 0x10,
	cuc_resume = 0x20,
	cuc_dump_addr = 0x40,
	cuc_dump_stats = 0x50,
	cuc_load_base = 0x60,
	cuc_dump_reset = 0x70,
};

enum cuc_dump
{
	cuc_dump_complete = 0xA005,
	cuc_dump_reset_complete = 0xA007,
};

enum port
{
	software_reset = 0x0,
	selftest = 0x1,
	selective_reset = 0x2,
};

/* eeprom control low */
enum eeprom_ctrl_low
{
		eesk = 0x1,
		eecs = 0x2,
		eedi = 0x4,
		eedo = 0x8,
};
/* Management Data Interface Control Register */
enum mdi_ctrl
{
		mdi_write = 0x4000000,
		mdi_read = 0x8000000,
		mdi_ready = 0x10000000,
};

/* eeprom operation */
enum eeprom_op
{
	op_write = 0x5,
	op_read = 0x6,
	op_ewds = 0x10,
	op_ewen = 0x13,
};

enum eeprom_offsets
{
	eeprom_cnfg_mdix = 0x3,
	eeprom_id = 0xa,
	eeprom_config_asf = 0xd,
	eeprom_smbus_addr = 0x90,
};

enum eeprom_cnfg_mdix
{
	eeprom_mdix_enabled = 0x80,
};

enum eeprom_id
{
	eeprom_id_wol = 0x20,	
};

enum eeprom_config_asf
{
	eeprom_asf = 0x8000,
	eeprom_gcl = 0x4000,
};

/* command block status */
enum cb_status
{
	cb_complete = 0x8000,
	cb_ok = 0x2000,
};

/* command block command */
enum cb_command
{
	cb_nop = 0x0,
	cb_iaaddr = 0x1,
	cb_config = 0x2,
	cb_multi = 0x3,
	cb_tx = 0x4,
	cb_ucode = 0x5,
	cb_dump = 0x6,
	cb_tx_sf = 0x8,
	cb_cid = 0x1f00,
	cb_i = 0x2000,
	cb_s = 0x4000,
	cb_el = 0x8000,
};

/* receive frame descriptor */
struct rfd
{
	u16 status;
	u16 command;
	u32 link;
	u32 rbd;
	u16 actual_size;
	u16 size;
};

/* receive buff*/
struct rx
{
	struct rx *next, *prev;
	struct sk_buff *skb;
	dma_addr_t dma_addr;
};

/* copy from drivers */
#if defined(__BIG_ENDIAN_BITFIELD)
#define X(a,b)	b,a
#else
#define X(a,b)	a,b
#endif
struct config {
/*0*/	u8 X(byte_count:6, pad0:2);
/*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
/*2*/	u8 adaptive_ifs;
/*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
	   term_write_cache_line:1), pad3:4);
/*4*/	u8 X(rx_dma_max_count:7, pad4:1);
/*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
/*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
	   rx_discard_overruns:1), rx_save_bad_frames:1);
/*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
	   tx_dynamic_tbd:1);
/*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
/*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);