📄 _primary.vhd
字号:
library verilog;use verilog.vl_types.all;entity I_Bus2Core is port( IWait : out vl_logic; Instruction : out vl_logic_vector(31 downto 0); in_InstructionAddress: in vl_logic_vector(31 downto 0); wb_ack_i : in vl_logic; wb_addr_o : out vl_logic_vector(31 downto 0); wb_cyc_o : out vl_logic; wb_data_i : in vl_logic_vector(31 downto 0); wb_data_o : out vl_logic_vector(31 downto 0); wb_err_i : in vl_logic; wb_rty_i : in vl_logic; wb_sel_o : out vl_logic_vector(7 downto 0); wb_stb_o : out vl_logic; wb_we_o : out vl_logic; clk_i : in vl_logic; rst_i : in vl_logic );end I_Bus2Core;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -