_primary.vhd

来自「mcu arm ,easy study and understand,for a」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity WordAdder is
    port(
        out_Result      : out    vl_logic_vector(31 downto 0);
        out_Carry       : out    vl_logic;
        out_Zero        : out    vl_logic;
        out_Neg         : out    vl_logic;
        out_Overflow    : out    vl_logic;
        in_LeftOperand  : in     vl_logic_vector(31 downto 0);
        in_RightOperand : in     vl_logic_vector(31 downto 0);
        in_LowCarry     : in     vl_logic
    );
end WordAdder;