_primary.vhd

mcu arm ,easy study and understand,for arm energer,it s very good.

library verilog;
use verilog.vl_types.all;
entity MEM is
    port(
        in_ALUValid     : in     vl_logic;
        in_ALUWriteBus  : in     vl_logic_vector(31 downto 0);
        in_ALUTargetRegister: in     vl_logic_vector(7 downto 0);
        in_SimpleALUResult: in     vl_logic_vector(31 downto 0);
        in_SimpleALUTargetRegister: in     vl_logic_vector(7 downto 0);
        in_StoredValue  : in     vl_logic_vector(31 downto 0);
        in_CPSR         : in     vl_logic_vector(31 downto 0);
        in_SPSR         : in     vl_logic_vector(31 downto 0);
        in_IfChangeState: in     vl_logic;
        in_ChangeStateAction: in     vl_logic_vector(4 downto 0);
        in_MEMStoreDelayBranchTarget: in     vl_logic;
        in_MEMDelayBranch: in     vl_logic;
        in_MemAccessUserBankRegister2MEM: in     vl_logic;
        in_MEMType      : in     vl_logic_vector(7 downto 0);
        in_MEMTargetRegister: in     vl_logic_vector(7 downto 0);
        in_SimpleMEMType: in     vl_logic_vector(7 downto 0);
        in_SimpleMEMTargetRegister: in     vl_logic_vector(7 downto 0);
        in_MEMPSRType   : in     vl_logic_vector(7 downto 0);
        in_IsLoadToPC   : in     vl_logic;
        out_MEMWriteEnable: out    vl_logic;
        out_MEMWriteResult: out    vl_logic_vector(31 downto 0);
        out_MEMTargetRegister: out    vl_logic_vector(7 downto 0);
        out_SimpleMEMResult: out    vl_logic_vector(31 downto 0);
        out_SimpleMEMTargetRegister: out    vl_logic_vector(7 downto 0);
        out_MEMPSRType2WB: out    vl_logic_vector(7 downto 0);
        out_CPSR2WB     : out    vl_logic_vector(31 downto 0);
        out_SPSR2WB     : out    vl_logic_vector(31 downto 0);
        out_IfChangeState: out    vl_logic;
        out_ChangeStateAction: out    vl_logic_vector(4 downto 0);
        out_MemAccessUserBankRegister2WB: out    vl_logic;
        out_WriteBus    : out    vl_logic_vector(31 downto 0);
        out_WriteRegisterEnable: out    vl_logic;
        out_WriteRegisterNumber: out    vl_logic_vector(7 downto 0);
        out_ThirdWriteBus: out    vl_logic_vector(31 downto 0);
        out_ThirdWriteRegisterEnable: out    vl_logic;
        out_ThirdWriteRegisterNumber: out    vl_logic_vector(7 downto 0);
        out_CPSR2PSR    : out    vl_logic_vector(31 downto 0);
        out_CPSRWriteEnable: out    vl_logic;
        out_SPSR2PSR    : out    vl_logic_vector(31 downto 0);
        out_SPSRWriteEnable: out    vl_logic;
        out_MEMOwnCanGo : out    vl_logic;
        in_EXECanGo     : in     vl_logic;
        out_MEMAccessAddress: out    vl_logic_vector(31 downto 0);
        out_MEMAccessRequest: out    vl_logic;
        out_MEMAccessRW : out    vl_logic;
        out_MEMAccessBW : out    vl_logic;
        in_DataCacheWait: in     vl_logic;
        in_DataBus      : in     vl_logic_vector(31 downto 0);
        out_DataBus     : out    vl_logic_vector(31 downto 0);
        out_MEMChangePC : out    vl_logic;
        out_MEMNewPC    : out    vl_logic_vector(31 downto 0);
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end MEM;