📄 lcd1.lst
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152 1 ;
153 1 ;-------------------------------------------------------
154 1 ; Oscillation stop detection register
155 1 ;-------------------------------------------------------
156 0000000Ch 1 cm2 .equ 000ch
157 1 ;
158 0,0000000Ch 1 cm20 .btequ 0,cm2 ; Oscillation stop detection bit
159 1,0000000Ch 1 cm21 .btequ 1,cm2 ; Main clock switch bit
160 2,0000000Ch 1 cm22 .btequ 2,cm2 ; Oscillation stop detection status
161 3,0000000Ch 1 cm23 .btequ 3,cm2 ; Clock monitor bit
162 7,0000000Ch 1 cm27 .btequ 7,cm2 ; Operation select bit(when an oscillation s
163 1 ;
164 1 ;-------------------------------------------------------
165 1 ; Watchdog timer start register
166 1 ;-------------------------------------------------------
167 0000000Eh 1 wdts .equ 000eh
168 1 ;
169 1 ;-------------------------------------------------------
170 1 ; Watchdog timer control register
171 1 ;-------------------------------------------------------
172 0000000Fh 1 wdc .equ 000fh
173 1 ;
174 5,0000000Fh 1 wdc5 .btequ 5,wdc ; Cold start / warm start discrimination fla
175 7,0000000Fh 1 wdc7 .btequ 7,wdc ; Prescaler select bit
176 1 ;
177 1 ;-------------------------------------------------------
178 1 ; Address match interrupt register 0
179 1 ;-------------------------------------------------------
180 00000010h 1 rmad0 .equ 0010h
181 00000010h 1 rmad0l .equ rmad0 ; Address match interrupt register 0L
182 00000011h 1 rmad0m .equ rmad0+1 ; Address match interrupt register 0M
183 00000012h 1 rmad0h .equ rmad0+2 ; Address match interrupt register 0H
184 1 ;
185 1 ;-------------------------------------------------------
186 1 ; Address match interrupt register 1
* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 004
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
187 1 ;-------------------------------------------------------
188 00000014h 1 rmad1 .equ 0014h
189 00000014h 1 rmad1l .equ rmad1 ; Address match interrupt register 1L
190 00000015h 1 rmad1m .equ rmad1+1 ; Address match interrupt register 1M
191 00000016h 1 rmad1h .equ rmad1+2 ; Address match interrupt register 1H
192 1 ;
193 1 ;-------------------------------------------------------
194 1 ; Power supply detection register 1
195 1 ;-------------------------------------------------------
196 00000019h 1 vcr1 .equ 0019h
197 1 ;
198 3,00000019h 1 vc13 .btequ 3,vcr1 ; Power supply down monitor flag
199 1 ;
200 1 ;-------------------------------------------------------
201 1 ; Power supply detection register 2
202 1 ;-------------------------------------------------------
203 0000001Ah 1 vcr2 .equ 001ah
204 1 ;
205 6,0000001Ah 1 vc26 .btequ 6,vcr2 ; Reset area monitor bit
206 7,0000001Ah 1 vc27 .btequ 7,vcr2 ; Power supply down monitor bit
207 1 ;
208 1 ;-------------------------------------------------------
209 1 ; Chip select expansion control register
210 1 ;-------------------------------------------------------
211 0000001Bh 1 cse .equ 001bh
212 1 ;
213 0,0000001Bh 1 cse00w .btequ 0,cse ; CS0~ wait expansion bit
214 1,0000001Bh 1 cse01w .btequ 1,cse ; CS0~ wait expansion bit
215 2,0000001Bh 1 cse10w .btequ 2,cse ; CS1~ wait expansion bit
216 3,0000001Bh 1 cse11w .btequ 3,cse ; CS1~ wait expansion bit
217 4,0000001Bh 1 cse20w .btequ 4,cse ; CS2~ wait expansion bit
218 5,0000001Bh 1 cse21w .btequ 5,cse ; CS2~ wait expansion bit
219 6,0000001Bh 1 cse30w .btequ 6,cse ; CS3~ wait expansion bit
220 7,0000001Bh 1 cse31w .btequ 7,cse ; CS3~ wait expansion bit
221 1 ;
222 1 ;-------------------------------------------------------
223 1 ; PLL control register 0
224 1 ;-------------------------------------------------------
225 0000001Ch 1 plc0 .equ 001ch
226 1 ;
227 0,0000001Ch 1 plc00 .btequ 0,plc0 ; Programmable counter select bit
228 1,0000001Ch 1 plc01 .btequ 1,plc0 ; Programmable counter select bit
229 2,0000001Ch 1 plc02 .btequ 2,plc0 ; Programmable counter select bit
230 7,0000001Ch 1 plc07 .btequ 7,plc0 ; Operation enable bit
231 1 ;
232 1 ;-------------------------------------------------------
233 1 ; Processor mode register 2
234 1 ;-------------------------------------------------------
235 0000001Eh 1 pm2 .equ 001eh
236 1 ;
237 0,0000001Eh 1 pm20 .btequ 0,pm2 ; Specifying wait when accessing SFR at PLL
238 1,0000001Eh 1 pm21 .btequ 1,pm2 ; System clock protective bit
239 2,0000001Eh 1 pm22 .btequ 2,pm2 ; WDT count source protective bit
240 1 ;
241 1 ;-------------------------------------------------------
242 1 ; Power supply down detection register
243 1 ;-------------------------------------------------------
244 0000001Fh 1 d4int .equ 001fh
245 1 ;
246 0,0000001Fh 1 d40 .btequ 0,d4int ; Power supply down detection interr
247 1,0000001Fh 1 d41 .btequ 1,d4int ; STOP mode deactivation control bit
248 2,0000001Fh 1 d42 .btequ 2,d4int ; Power supply change detection flag
* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 005
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
249 3,0000001Fh 1 d43 .btequ 3,d4int ; WDT overflow detect flag
250 4,0000001Fh 1 df0 .btequ 4,d4int ; Sampling clock select bit
251 5,0000001Fh 1 df1 .btequ 5,d4int ; Sampling clock select bit
252 1 ;
253 1 ;-------------------------------------------------------
254 1 ; DMA0 source pointer
255 1 ;-------------------------------------------------------
256 00000020h 1 sar0 .equ 0020h
257 1 ;
258 00000020h 1 sar0l .equ sar0 ; DMA0 source pointer L
259 00000021h 1 sar0m .equ sar0+1 ; DMA0 source pointer M
260 00000022h 1 sar0h .equ sar0+2 ; DMA0 source pointer H
261 1 ;
262 1 ;-------------------------------------------------------
263 1 ; DMA0 destination pointer
264 1 ;-------------------------------------------------------
265 00000024h 1 dar0 .equ 0024h
266 1 ;
267 00000024h 1 dar0l .equ dar0 ; DMA0 destination pointer L
268 00000025h 1 dar0m .equ dar0+1 ; DMA0 destination pointer M
269 00000026h 1 dar0h .equ dar0+2 ; DMA0 destination pointer H
270 1 ;
271 1 ;-------------------------------------------------------
272 1 ; DMA0 transfer counter
273 1 ;-------------------------------------------------------
274 00000028h 1 tcr0 .equ 0028h
275 1 ;
276 00000028h 1 tcr0l .equ tcr0 ; DMA0 transfer counter L
277 00000029h 1 tcr0h .equ tcr0+1 ; DMA0 transfer counter H
278 1 ;
279 1 ;-------------------------------------------------------
280 1 ; DMA0 control register
281 1 ;-------------------------------------------------------
282 0000002Ch 1 dm0con .equ 002ch
283 1 ;
284 0,0000002Ch 1 dmbit_dm0con .btequ 0,dm0con ; Transfer unit bit select bit
285 1,0000002Ch 1 dmasl_dm0con .btequ 1,dm0con ; Repeat transfer mode select bit
286 2,0000002Ch 1 dmas_dm0con .btequ 2,dm0con ; DMA request bit
287 3,0000002Ch 1 dmae_dm0con .btequ 3,dm0con ; DMA enable bit
288 4,0000002Ch 1 dsd_dm0con .btequ 4,dm0con ; Source address direction select bit
289 5,0000002Ch 1 dad_dm0con .btequ 5,dm0con ; Destination address direction select bit
290 1 ;
291 1 ;-------------------------------------------------------
292 1 ; DMA1 source pointer
293 1 ;-------------------------------------------------------
294 00000030h 1 sar1 .equ 0030h
295 1 ;
296 00000030h 1 sar1l .equ sar1 ; DMA1 source pointer L
297 00000031h 1 sar1m .equ sar1+1 ; DMA1 source pointer M
298 00000032h 1 sar1h .equ sar1+2 ; DMA1 source pointer H
299 1 ;
300 1 ;-------------------------------------------------------
301 1 ; DMA1 destination pointer
302 1 ;-------------------------------------------------------
303 00000034h 1 dar1 .equ 0034h
304 1 ;
305 00000034h 1 dar1l .equ dar1 ; DMA1 destination pointer L
306 00000035h 1 dar1m .equ dar1+1 ; DMA1 destination pointer M
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