📄 lcd1.lst
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* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 001
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
1 ;""FILE COMMENT""**************************************************************
2 ; System Name : for eduction (NO TRANSFERRING)
3 ; File Name : lcd1.a30
4 ; Contents : the low level program used by LCD(assembly language)
5 ; Model : for OAKS8-LCD Board
6 ; CPU : R8C/Tiny series
7 ; Assembler : as30(V.5.10.00)
8 ; Linker : ln30(V.5.10.0)
9 ; Programer : RENESAS Semiconductor Training Center
10 ; Note : for OAKS8-R5F21114FP(R8C/11 group,20MHz)
11 ; : for SC1602BS*B material
12 ;******************************************************************************
13 ; COPYRIGHT(C) 2004 RENESAS TECHNOLOGY CORPORATION
14 ; AND RENESAS SOLUTIONS CORPORATION ALL RIGHTS RESERVED
15 ;******************************************************************************
16 ; History : ---
17 ;""FILE COMMENT END""**********************************************************
18
19 .include ..\library\sfr62p.inc ; for M16C/60 series
20 1 ;************************************************************************************
21 1 ;*
22 1 ;* file name : definition of M16C/62P's SFR
23 1 ;*
24 1 ;* Copyright, 2005 RENESAS TECHNOLOGY CORPORATION
25 1 ;* AND RENESAS SOLUTIONS CORPORATION
26 1 ;*
27 1 ;* Version : 1.00 ( 2002- 7-22 ) Initial
28 1 ;* : 2.00 ( 2002-12-27 )
29 1 ;* : cm3 register delete
30 1 ;* : vcr1 register add
31 1 ;* : vcr2 register add
32 1 ;* : d4int register add
33 1 ;* : u1bcnic register add
34 1 ;* : u0bcnic register add
35 1 ;* : wdc5 bit add (wdc register)
36 1 ;* : plc06 bit add (plc0 register)
37 1 ;* : pm21 bit add (pm2 register)
38 1 ;* : pm22 bit add (pm2 register)
39 1 ;* : fidr register
40 1 ;* : 3B4h => 1B4h
41 1 ;* : fmr03 bit delete (fmr0 register)
42 1 ;* : fmstp bit add (fmr0 register)
43 1 ;* : 2.02 ( 2004-04-16 )
44 1 ;* : prc3 bit add (prcr register)
45 1 ;* : 2.10 ( 2005-06-06 )
46 1 ;* : vc25 bit delete (vcr2 register)
47 1 ;* : inv17 bit delete (invc1 register)
48 1 ;* : lsyn_u0smr bit delete (u0smr register)
49 1 ;* : lsyn_u1smr bit delete (u1smr register)
50 1 ;* : lsyn_u2smr bit delete (u2smr register)
51 1 ;*
52 1 ;************************************************************************************
53 1 ;
54 1 ; note:
55 1 ; This data is a freeware that SFR for M16C/62P groups is described.
56 1 ; Renesas Technology Corporation and Renesas Solutions Corporation
57 1 ; assumes no responsibility for any damage that occurred by this data.
58 1 ;
59 1 ;-------------------------------------------------------
60 1 ; Processor mode register 0
61 1 ;-------------------------------------------------------
62 00000004h 1 pm0 .equ 0004h
* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 002
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
63 1 ;
64 0,00000004h 1 pm00 .btequ 0,pm0 ; Processor mode bit
65 1,00000004h 1 pm01 .btequ 1,pm0 ; Processor mode bit
66 2,00000004h 1 pm02 .btequ 2,pm0 ; R/W mode select bit
67 3,00000004h 1 pm03 .btequ 3,pm0 ; Software reset bit
68 4,00000004h 1 pm04 .btequ 4,pm0 ; Multiplexed bus space select bit
69 5,00000004h 1 pm05 .btequ 5,pm0 ; Multiplexed bus space select bit
70 6,00000004h 1 pm06 .btequ 6,pm0 ; Port P4_0 to P4_3 function select bit
71 7,00000004h 1 pm07 .btequ 7,pm0 ; BCLK output disable bit
72 1 ;
73 1 ;-------------------------------------------------------
74 1 ; Processor mode register 1
75 1 ;-------------------------------------------------------
76 00000005h 1 pm1 .equ 0005h
77 1 ;
78 0,00000005h 1 pm10 .btequ 0,pm1 ; CS2 area switching bit
79 1,00000005h 1 pm11 .btequ 1,pm1 ; Port P3_4 to P3_7 function select bit
80 2,00000005h 1 pm12 .btequ 2,pm1 ; Watch dog timer function select bit
81 3,00000005h 1 pm13 .btequ 3,pm1 ; Internal reserved area expansion bit
82 4,00000005h 1 pm14 .btequ 4,pm1 ; Memory area expansion bit
83 5,00000005h 1 pm15 .btequ 5,pm1 ; Memory area expansion bit
84 7,00000005h 1 pm17 .btequ 7,pm1 ; Wait bit
85 1 ;
86 1 ;-------------------------------------------------------
87 1 ; System clock control register 0
88 1 ;-------------------------------------------------------
89 00000006h 1 cm0 .equ 0006h
90 1 ;
91 0,00000006h 1 cm00 .btequ 0,cm0 ; Clock output function select bit
92 1,00000006h 1 cm01 .btequ 1,cm0 ; Clock output function select bit
93 2,00000006h 1 cm02 .btequ 2,cm0 ; WAIT peripheral function clock stop bit
94 3,00000006h 1 cm03 .btequ 3,cm0 ; Xcin-Xcout drive capacity select bit
95 4,00000006h 1 cm04 .btequ 4,cm0 ; Port Xc select bit
96 5,00000006h 1 cm05 .btequ 5,cm0 ; Main clock stop bit
97 6,00000006h 1 cm06 .btequ 6,cm0 ; Main clock division select bit 0
98 7,00000006h 1 cm07 .btequ 7,cm0 ; System clock select bit
99 1 ;
100 1 ;-------------------------------------------------------
101 1 ; System clock control register 1
102 1 ;-------------------------------------------------------
103 00000007h 1 cm1 .equ 0007h
104 1 ;
105 0,00000007h 1 cm10 .btequ 0,cm1 ; All clock stop control bit
106 1,00000007h 1 cm11 .btequ 1,cm1 ; System clock select bit
107 5,00000007h 1 cm15 .btequ 5,cm1 ; Xin-Xout drive capacity select bit
108 6,00000007h 1 cm16 .btequ 6,cm1 ; Main clock division select bit 1
109 7,00000007h 1 cm17 .btequ 7,cm1 ; Main clock division select bit 1
110 1 ;
111 1 ;-------------------------------------------------------
112 1 ; Chip select control register
113 1 ;-------------------------------------------------------
114 00000008h 1 csr .equ 0008h
115 1 ;
116 0,00000008h 1 cs0 .btequ 0,csr ; CS0~ output enable bit
117 1,00000008h 1 cs1 .btequ 1,csr ; CS1~ output enable bit
118 2,00000008h 1 cs2 .btequ 2,csr ; CS2~ output enable bit
119 3,00000008h 1 cs3 .btequ 3,csr ; CS3~ output enable bit
120 4,00000008h 1 cs0w .btequ 4,csr ; CS0~ wait bit
121 5,00000008h 1 cs1w .btequ 5,csr ; CS1~ wait bit
122 6,00000008h 1 cs2w .btequ 6,csr ; CS2~ wait bit
123 7,00000008h 1 cs3w .btequ 7,csr ; CS3~ wait bit
124 1 ;
* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 003
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
125 1 ;-------------------------------------------------------
126 1 ; Address match interrupt enable register
127 1 ;-------------------------------------------------------
128 00000009h 1 aier .equ 0009h
129 1 ;
130 0,00000009h 1 aier0 .btequ 0,aier ; Address match interrupt 0 enable bit
131 1,00000009h 1 aier1 .btequ 1,aier ; Address match interrupt 1 enable bit
132 1 ;
133 1 ;-------------------------------------------------------
134 1 ; Protect register
135 1 ;-------------------------------------------------------
136 0000000Ah 1 prcr .equ 000ah
137 1 ;
138 0,0000000Ah 1 prc0 .btequ 0,prcr ; Enable writting to system clock control re
139 1,0000000Ah 1 prc1 .btequ 1,prcr ; Enable writting to processor mode register
140 2,0000000Ah 1 prc2 .btequ 2,prcr ; Enable writting to port P9 direction regis
141 3,0000000Ah 1 prc3 .btequ 3,prcr ; Enable writting to Power supply detection
142 1 ;
143 1 ;-------------------------------------------------------
144 1 ; Data bank register
145 1 ;-------------------------------------------------------
146 0000000Bh 1 dbr .equ 000bh
147 1 ;
148 2,0000000Bh 1 ofs .btequ 2,dbr ; Off set bit
149 3,0000000Bh 1 bsr0 .btequ 3,dbr ; Bank select bit
150 4,0000000Bh 1 bsr1 .btequ 4,dbr ; Bank select bit
151 5,0000000Bh 1 bsr2 .btequ 5,dbr ; Bank select bit
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