📄 ncrt0.lst
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152 1 ;
153 0,0000000Ch 1 cm20 .btequ 0,cm2 ; Oscillation stop detection bit
154 1,0000000Ch 1 cm21 .btequ 1,cm2 ; Main clock switch bit
155 2,0000000Ch 1 cm22 .btequ 2,cm2 ; Oscillation stop detection status
156 3,0000000Ch 1 cm23 .btequ 3,cm2 ; Clock monitor bit
157 7,0000000Ch 1 cm27 .btequ 7,cm2 ; Operation select bit(when an oscillation s
158 1 ;
159 1 ;-------------------------------------------------------
160 1 ; Watchdog timer start register
161 1 ;-------------------------------------------------------
162 0000000Eh 1 wdts .equ 000eh
163 1 ;
164 1 ;-------------------------------------------------------
165 1 ; Watchdog timer control register
166 1 ;-------------------------------------------------------
167 0000000Fh 1 wdc .equ 000fh
168 1 ;
169 5,0000000Fh 1 wdc5 .btequ 5,wdc ; Cold start / warm start discrimination fla
170 7,0000000Fh 1 wdc7 .btequ 7,wdc ; Prescaler select bit
171 1 ;
172 1 ;-------------------------------------------------------
173 1 ; Address match interrupt register 0
174 1 ;-------------------------------------------------------
175 00000010h 1 rmad0 .equ 0010h
176 00000010h 1 rmad0l .equ rmad0 ; Address match interrupt register 0L
177 00000011h 1 rmad0m .equ rmad0+1 ; Address match interrupt register 0M
178 00000012h 1 rmad0h .equ rmad0+2 ; Address match interrupt register 0H
179 1 ;
180 1 ;-------------------------------------------------------
181 1 ; Address match interrupt register 1
182 1 ;-------------------------------------------------------
183 00000014h 1 rmad1 .equ 0014h
184 00000014h 1 rmad1l .equ rmad1 ; Address match interrupt register 1L
185 00000015h 1 rmad1m .equ rmad1+1 ; Address match interrupt register 1M
186 00000016h 1 rmad1h .equ rmad1+2 ; Address match interrupt register 1H
* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 004
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
187 1 ;
188 1 ;-------------------------------------------------------
189 1 ; Power supply detection register 1
190 1 ;-------------------------------------------------------
191 00000019h 1 vcr1 .equ 0019h
192 1 ;
193 3,00000019h 1 vc13 .btequ 3,vcr1 ; Power supply down monitor flag
194 1 ;
195 1 ;-------------------------------------------------------
196 1 ; Power supply detection register 2
197 1 ;-------------------------------------------------------
198 0000001Ah 1 vcr2 .equ 001ah
199 1 ;
200 6,0000001Ah 1 vc26 .btequ 6,vcr2 ; Reset area monitor bit
201 7,0000001Ah 1 vc27 .btequ 7,vcr2 ; Power supply down monitor bit
202 1 ;
203 1 ;-------------------------------------------------------
204 1 ; Chip select expansion control register
205 1 ;-------------------------------------------------------
206 0000001Bh 1 cse .equ 001bh
207 1 ;
208 0,0000001Bh 1 cse00w .btequ 0,cse ; CS0~ wait expansion bit
209 1,0000001Bh 1 cse01w .btequ 1,cse ; CS0~ wait expansion bit
210 2,0000001Bh 1 cse10w .btequ 2,cse ; CS1~ wait expansion bit
211 3,0000001Bh 1 cse11w .btequ 3,cse ; CS1~ wait expansion bit
212 4,0000001Bh 1 cse20w .btequ 4,cse ; CS2~ wait expansion bit
213 5,0000001Bh 1 cse21w .btequ 5,cse ; CS2~ wait expansion bit
214 6,0000001Bh 1 cse30w .btequ 6,cse ; CS3~ wait expansion bit
215 7,0000001Bh 1 cse31w .btequ 7,cse ; CS3~ wait expansion bit
216 1 ;
217 1 ;-------------------------------------------------------
218 1 ; PLL control register 0
219 1 ;-------------------------------------------------------
220 0000001Ch 1 plc0 .equ 001ch
221 1 ;
222 0,0000001Ch 1 plc00 .btequ 0,plc0 ; Programmable counter select bit
223 1,0000001Ch 1 plc01 .btequ 1,plc0 ; Programmable counter select bit
224 2,0000001Ch 1 plc02 .btequ 2,plc0 ; Programmable counter select bit
225 7,0000001Ch 1 plc07 .btequ 7,plc0 ; Operation enable bit
226 1 ;
227 1 ;-------------------------------------------------------
228 1 ; Processor mode register 2
229 1 ;-------------------------------------------------------
230 0000001Eh 1 pm2 .equ 001eh
231 1 ;
232 0,0000001Eh 1 pm20 .btequ 0,pm2 ; Specifying wait when accessing SFR at PLL
233 1,0000001Eh 1 pm21 .btequ 1,pm2 ; System clock protective bit
234 2,0000001Eh 1 pm22 .btequ 2,pm2 ; WDT count source protective bit
235 1 ;
236 1 ;-------------------------------------------------------
237 1 ; Power supply down detection register
238 1 ;-------------------------------------------------------
239 0000001Fh 1 d4int .equ 001fh
240 1 ;
241 0,0000001Fh 1 d40 .btequ 0,d4int ; Power supply down detection interr
242 1,0000001Fh 1 d41 .btequ 1,d4int ; STOP mode deactivation control bit
243 2,0000001Fh 1 d42 .btequ 2,d4int ; Power supply change detection flag
244 3,0000001Fh 1 d43 .btequ 3,d4int ; WDT overflow detect flag
245 4,0000001Fh 1 df0 .btequ 4,d4int ; Sampling clock select bit
246 5,0000001Fh 1 df1 .btequ 5,d4int ; Sampling clock select bit
247 1 ;
248 1 ;-------------------------------------------------------
* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 005
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
249 1 ; DMA0 source pointer
250 1 ;-------------------------------------------------------
251 00000020h 1 sar0 .equ 0020h
252 1 ;
253 00000020h 1 sar0l .equ sar0 ; DMA0 source pointer L
254 00000021h 1 sar0m .equ sar0+1 ; DMA0 source pointer M
255 00000022h 1 sar0h .equ sar0+2 ; DMA0 source pointer H
256 1 ;
257 1 ;-------------------------------------------------------
258 1 ; DMA0 destination pointer
259 1 ;-------------------------------------------------------
260 00000024h 1 dar0 .equ 0024h
261 1 ;
262 00000024h 1 dar0l .equ dar0 ; DMA0 destination pointer L
263 00000025h 1 dar0m .equ dar0+1 ; DMA0 destination pointer M
264 00000026h 1 dar0h .equ dar0+2 ; DMA0 destination pointer H
265 1 ;
266 1 ;-------------------------------------------------------
267 1 ; DMA0 transfer counter
268 1 ;-------------------------------------------------------
269 00000028h 1 tcr0 .equ 0028h
270 1 ;
271 00000028h 1 tcr0l .equ tcr0 ; DMA0 transfer counter L
272 00000029h 1 tcr0h .equ tcr0+1 ; DMA0 transfer counter H
273 1 ;
274 1 ;-------------------------------------------------------
275 1 ; DMA0 control register
276 1 ;-------------------------------------------------------
277 0000002Ch 1 dm0con .equ 002ch
278 1 ;
279 0,0000002Ch 1 dmbit_dm0con .btequ 0,dm0con ; Transfer unit bit select bit
280 1,0000002Ch 1 dmasl_dm0con .btequ 1,dm0con ; Repeat transfer mode select bit
281 2,0000002Ch 1 dmas_dm0con .btequ 2,dm0con ; DMA request bit
282 3,0000002Ch 1 dmae_dm0con .btequ 3,dm0con ; DMA enable bit
283 4,0000002Ch 1 dsd_dm0con .btequ 4,dm0con ; Source address direction select bit
284 5,0000002Ch 1 dad_dm0con .btequ 5,dm0con ; Destination address direction select bit
285 1 ;
286 1 ;-------------------------------------------------------
287 1 ; DMA1 source pointer
288 1 ;-------------------------------------------------------
289 00000030h 1 sar1 .equ 0030h
290 1 ;
291 00000030h 1 sar1l .equ sar1 ; DMA1 source pointer L
292 00000031h 1 sar1m .equ sar1+1 ; DMA1 source pointer M
293 00000032h 1 sar1h .equ sar1+2 ; DMA1 source pointer H
294 1 ;
295 1 ;-------------------------------------------------------
296 1 ; DMA1 destination pointer
297 1 ;-------------------------------------------------------
298 00000034h 1 dar1 .equ 0034h
299 1 ;
300 00000034h 1 dar1l .equ dar1 ; DMA1 destination pointer L
301 00000035h 1 dar1m .equ dar1+1 ; DMA1 destination pointer M
302 00000036h 1 dar1h .equ dar1+2 ; DMA1 destination pointer H
303 1 ;
304 1 ;-------------------------------------------------------
305 1 ; DMA1 transfer counter
306 1 ;-------------------------------------------------------
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