📄 ncrt0.lst
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* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 001
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
1 ;*************************************************************************** ;
2 ; C COMPILER for R8C/Tiny, M16C/60,30,20,10
3 ; Copyright(C) 1999(2000-2004). Renesas Technology Corp.
4 ; and Renesas Solutions Corp., All rights reserved.
5 ;
6 ;
7 ; ncrt0.a30 : NC30 startup program
8 ;
9 ; This program is applicable when using the basic I/O library
10 ;
11 ; $Id: ncrt0.a30,v 1.27.4.4 2004/10/29 14:06:38 simomura Exp $
12 ;
13 ;***************************************************************************
14 .include ..\library\sfr62p.inc
15 1 ;************************************************************************************
16 1 ;*
17 1 ;* file name : definition of M16C/62P's SFR
18 1 ;*
19 1 ;* Copyright, 2005 RENESAS TECHNOLOGY CORPORATION
20 1 ;* AND RENESAS SOLUTIONS CORPORATION
21 1 ;*
22 1 ;* Version : 1.00 ( 2002- 7-22 ) Initial
23 1 ;* : 2.00 ( 2002-12-27 )
24 1 ;* : cm3 register delete
25 1 ;* : vcr1 register add
26 1 ;* : vcr2 register add
27 1 ;* : d4int register add
28 1 ;* : u1bcnic register add
29 1 ;* : u0bcnic register add
30 1 ;* : wdc5 bit add (wdc register)
31 1 ;* : plc06 bit add (plc0 register)
32 1 ;* : pm21 bit add (pm2 register)
33 1 ;* : pm22 bit add (pm2 register)
34 1 ;* : fidr register
35 1 ;* : 3B4h => 1B4h
36 1 ;* : fmr03 bit delete (fmr0 register)
37 1 ;* : fmstp bit add (fmr0 register)
38 1 ;* : 2.02 ( 2004-04-16 )
39 1 ;* : prc3 bit add (prcr register)
40 1 ;* : 2.10 ( 2005-06-06 )
41 1 ;* : vc25 bit delete (vcr2 register)
42 1 ;* : inv17 bit delete (invc1 register)
43 1 ;* : lsyn_u0smr bit delete (u0smr register)
44 1 ;* : lsyn_u1smr bit delete (u1smr register)
45 1 ;* : lsyn_u2smr bit delete (u2smr register)
46 1 ;*
47 1 ;************************************************************************************
48 1 ;
49 1 ; note:
50 1 ; This data is a freeware that SFR for M16C/62P groups is described.
51 1 ; Renesas Technology Corporation and Renesas Solutions Corporation
52 1 ; assumes no responsibility for any damage that occurred by this data.
53 1 ;
54 1 ;-------------------------------------------------------
55 1 ; Processor mode register 0
56 1 ;-------------------------------------------------------
57 00000004h 1 pm0 .equ 0004h
58 1 ;
59 0,00000004h 1 pm00 .btequ 0,pm0 ; Processor mode bit
60 1,00000004h 1 pm01 .btequ 1,pm0 ; Processor mode bit
61 2,00000004h 1 pm02 .btequ 2,pm0 ; R/W mode select bit
62 3,00000004h 1 pm03 .btequ 3,pm0 ; Software reset bit
* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 002
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
63 4,00000004h 1 pm04 .btequ 4,pm0 ; Multiplexed bus space select bit
64 5,00000004h 1 pm05 .btequ 5,pm0 ; Multiplexed bus space select bit
65 6,00000004h 1 pm06 .btequ 6,pm0 ; Port P4_0 to P4_3 function select bit
66 7,00000004h 1 pm07 .btequ 7,pm0 ; BCLK output disable bit
67 1 ;
68 1 ;-------------------------------------------------------
69 1 ; Processor mode register 1
70 1 ;-------------------------------------------------------
71 00000005h 1 pm1 .equ 0005h
72 1 ;
73 0,00000005h 1 pm10 .btequ 0,pm1 ; CS2 area switching bit
74 1,00000005h 1 pm11 .btequ 1,pm1 ; Port P3_4 to P3_7 function select bit
75 2,00000005h 1 pm12 .btequ 2,pm1 ; Watch dog timer function select bit
76 3,00000005h 1 pm13 .btequ 3,pm1 ; Internal reserved area expansion bit
77 4,00000005h 1 pm14 .btequ 4,pm1 ; Memory area expansion bit
78 5,00000005h 1 pm15 .btequ 5,pm1 ; Memory area expansion bit
79 7,00000005h 1 pm17 .btequ 7,pm1 ; Wait bit
80 1 ;
81 1 ;-------------------------------------------------------
82 1 ; System clock control register 0
83 1 ;-------------------------------------------------------
84 00000006h 1 cm0 .equ 0006h
85 1 ;
86 0,00000006h 1 cm00 .btequ 0,cm0 ; Clock output function select bit
87 1,00000006h 1 cm01 .btequ 1,cm0 ; Clock output function select bit
88 2,00000006h 1 cm02 .btequ 2,cm0 ; WAIT peripheral function clock stop bit
89 3,00000006h 1 cm03 .btequ 3,cm0 ; Xcin-Xcout drive capacity select bit
90 4,00000006h 1 cm04 .btequ 4,cm0 ; Port Xc select bit
91 5,00000006h 1 cm05 .btequ 5,cm0 ; Main clock stop bit
92 6,00000006h 1 cm06 .btequ 6,cm0 ; Main clock division select bit 0
93 7,00000006h 1 cm07 .btequ 7,cm0 ; System clock select bit
94 1 ;
95 1 ;-------------------------------------------------------
96 1 ; System clock control register 1
97 1 ;-------------------------------------------------------
98 00000007h 1 cm1 .equ 0007h
99 1 ;
100 0,00000007h 1 cm10 .btequ 0,cm1 ; All clock stop control bit
101 1,00000007h 1 cm11 .btequ 1,cm1 ; System clock select bit
102 5,00000007h 1 cm15 .btequ 5,cm1 ; Xin-Xout drive capacity select bit
103 6,00000007h 1 cm16 .btequ 6,cm1 ; Main clock division select bit 1
104 7,00000007h 1 cm17 .btequ 7,cm1 ; Main clock division select bit 1
105 1 ;
106 1 ;-------------------------------------------------------
107 1 ; Chip select control register
108 1 ;-------------------------------------------------------
109 00000008h 1 csr .equ 0008h
110 1 ;
111 0,00000008h 1 cs0 .btequ 0,csr ; CS0~ output enable bit
112 1,00000008h 1 cs1 .btequ 1,csr ; CS1~ output enable bit
113 2,00000008h 1 cs2 .btequ 2,csr ; CS2~ output enable bit
114 3,00000008h 1 cs3 .btequ 3,csr ; CS3~ output enable bit
115 4,00000008h 1 cs0w .btequ 4,csr ; CS0~ wait bit
116 5,00000008h 1 cs1w .btequ 5,csr ; CS1~ wait bit
117 6,00000008h 1 cs2w .btequ 6,csr ; CS2~ wait bit
118 7,00000008h 1 cs3w .btequ 7,csr ; CS3~ wait bit
119 1 ;
120 1 ;-------------------------------------------------------
121 1 ; Address match interrupt enable register
122 1 ;-------------------------------------------------------
123 00000009h 1 aier .equ 0009h
124 1 ;
* R8C/Tiny,M16C/60 SERIES ASSEMBLER * SOURCE LIST Fri Jun 09 17:26:28 2006 PAGE 003
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
125 0,00000009h 1 aier0 .btequ 0,aier ; Address match interrupt 0 enable bit
126 1,00000009h 1 aier1 .btequ 1,aier ; Address match interrupt 1 enable bit
127 1 ;
128 1 ;-------------------------------------------------------
129 1 ; Protect register
130 1 ;-------------------------------------------------------
131 0000000Ah 1 prcr .equ 000ah
132 1 ;
133 0,0000000Ah 1 prc0 .btequ 0,prcr ; Enable writting to system clock control re
134 1,0000000Ah 1 prc1 .btequ 1,prcr ; Enable writting to processor mode register
135 2,0000000Ah 1 prc2 .btequ 2,prcr ; Enable writting to port P9 direction regis
136 3,0000000Ah 1 prc3 .btequ 3,prcr ; Enable writting to Power supply detection
137 1 ;
138 1 ;-------------------------------------------------------
139 1 ; Data bank register
140 1 ;-------------------------------------------------------
141 0000000Bh 1 dbr .equ 000bh
142 1 ;
143 2,0000000Bh 1 ofs .btequ 2,dbr ; Off set bit
144 3,0000000Bh 1 bsr0 .btequ 3,dbr ; Bank select bit
145 4,0000000Bh 1 bsr1 .btequ 4,dbr ; Bank select bit
146 5,0000000Bh 1 bsr2 .btequ 5,dbr ; Bank select bit
147 1 ;
148 1 ;-------------------------------------------------------
149 1 ; Oscillation stop detection register
150 1 ;-------------------------------------------------------
151 0000000Ch 1 cm2 .equ 000ch
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