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📄 test_int0.ls1

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----                 198     CSEG    AT      00003H
0003 020000   F      199             LJMP    int00
                     200     
                     201     ; void int00() interrupt 0 using 0
                     202     
----                 203             RSEG  ?PR?int00?TEST_INT0
                     204             USING   0
0000                 205     int00:
                     206                             ; SOURCE LINE # 20
                     207     ; {
                     208     ;       TR1=1;
                     209                             ; SOURCE LINE # 22
0000 D28E            210             SETB    TR1
                     211     ;       bufth0=TH0;buftl0=TL0;bufn0=n0;
                     212                             ; SOURCE LINE # 23
0002 858C00   F      213             MOV     bufth0,TH0
0005 858A00   F      214             MOV     buftl0,TL0
0008 850000   F      215             MOV     bufn0,n0
                     216     ;       TH0=0;TL0=0;n0=0;
                     217                             ; SOURCE LINE # 24
000B 758C00          218             MOV     TH0,#00H
000E 758A00          219             MOV     TL0,#00H
0011 750000   F      220             MOV     n0,#00H
                     221     ;       flag_over0=1; 
                     222                             ; SOURCE LINE # 25
0014 D200     F      223             SETB    flag_over0
                     224     ; }
                     225                             ; SOURCE LINE # 26
0016 32              226             RETI    
                     227     ; END OF int00
                     228     
----                 229     CSEG    AT      00013H
0013 020000   F      230             LJMP    int11
                     231     
                     232     ; 
                     233     ; void int11() interrupt 2 using 2
                     234     
----                 235             RSEG  ?PR?int11?TEST_INT0
                     236             USING   2
0000                 237     int11:
                     238                             ; SOURCE LINE # 28
                     239     ; {     TR1=0;
                     240                             ; SOURCE LINE # 29
0000 C28E            241             CLR     TR1
                     242     ;       BUFTH1=TH1;BUFTL1=TL1;BUFn1=n1;
                     243                             ; SOURCE LINE # 30
0002 858D00   F      244             MOV     BUFTH1,TH1
0005 858B00   F      245             MOV     BUFTL1,TL1
0008 850000   F      246             MOV     BUFn1,n1
                     247     ;       TH1=0;TL1=0;n1=0;
                     248                             ; SOURCE LINE # 31
000B 758D00          249             MOV     TH1,#00H
000E 758B00          250             MOV     TL1,#00H
0011 750000   F      251             MOV     n1,#00H
                     252     ;       flag_over1=1;
                     253                             ; SOURCE LINE # 32
0014 D200     F      254             SETB    flag_over1
                     255     ; }
A51 MACRO ASSEMBLER  TEST_INT0                                                            03/20/2009 23:30:11 PAGE     5

                     256                             ; SOURCE LINE # 33
0016 32              257             RETI    
                     258     ; END OF int11
                     259     
----                 260     CSEG    AT      0000BH
000B 020000   F      261             LJMP    time0
                     262     
                     263     ; 
                     264     ; void time0() interrupt 1 using 1
                     265     
----                 266             RSEG  ?PR?time0?TEST_INT0
                     267             USING   1
0000                 268     time0:
                     269                             ; SOURCE LINE # 35
                     270     ; {n0++;countn0++;}
                     271                             ; SOURCE LINE # 36
0000 0500     F      272             INC     n0
0002 0500     F      273             INC     countn0
0004 32              274             RETI    
                     275     ; END OF time0
                     276     
----                 277     CSEG    AT      0001BH
001B 020000   F      278             LJMP    time1
                     279     
                     280     ; 
                     281     ; void time1() interrupt 3 using 3 
                     282     
----                 283             RSEG  ?PR?time1?TEST_INT0
                     284             USING   3
0000                 285     time1:
                     286                             ; SOURCE LINE # 38
                     287     ; {n1++;}
                     288                             ; SOURCE LINE # 39
0000 0500     F      289             INC     n1
0002 32              290             RETI    
                     291     ; END OF time1
                     292     
----                 293     CSEG    AT      0002BH
002B 020000   F      294             LJMP    time2
                     295     
                     296     ; 
                     297     ; void time2() interrupt 5 using 3
                     298     
----                 299             RSEG  ?PR?time2?TEST_INT0
                     300             USING   3
0000                 301     time2:
0000 C0E0            302             PUSH    ACC
0002 C0F0            303             PUSH    B
0004 C083            304             PUSH    DPH
0006 C082            305             PUSH    DPL
0008 C0D0            306             PUSH    PSW
                     307             USING   3
000A 75D018          308             MOV     PSW,#018H
                     309                             ; SOURCE LINE # 41
                     310     ; {
                     311     ;       TF2=0;
                     312                             ; SOURCE LINE # 43
000D C2CF            313             CLR     TF2
                     314     ;       if(flag_countT0)
                     315                             ; SOURCE LINE # 44
000F 300013   F      316             JNB     flag_countT0,?C0005
                     317     ;       {       TIME1S_count++;
                     318                             ; SOURCE LINE # 45
0012 0500     F      319             INC     TIME1S_count
                     320     ;               if(TIME1S_count==170)
                     321                             ; SOURCE LINE # 46
A51 MACRO ASSEMBLER  TEST_INT0                                                            03/20/2009 23:30:11 PAGE     6

0014 E500     F      322             MOV     A,TIME1S_count
0016 B4AA07          323             CJNE    A,#0AAH,?C0006
                     324     ;                       {TR0=0;TIME1S_count=0;flag1s=1;}
                     325                             ; SOURCE LINE # 47
0019 C28C            326             CLR     TR0
001B 750000   F      327             MOV     TIME1S_count,#00H
001E D200     F      328             SETB    flag1s
0020                 329     ?C0006:
                     330     ;               display();
                     331                             ; SOURCE LINE # 48
0020 120000   F      332             LCALL   display
                     333     ;       }
                     334                             ; SOURCE LINE # 49
0023 800C            335             SJMP    ?C0009
0025                 336     ?C0005:
                     337     ;       else
                     338     ;       {       TIME0_5S_count++;
                     339                             ; SOURCE LINE # 51
0025 0500     F      340             INC     TIME0_5S_count
                     341     ;               if(TIME0_5S_count==80)
                     342                             ; SOURCE LINE # 52
0027 E500     F      343             MOV     A,TIME0_5S_count
0029 B45005          344             CJNE    A,#050H,?C0009
                     345     ;               {TIME0_5S_count=0;flag0_5s=1;}
                     346                             ; SOURCE LINE # 53
002C 750000   F      347             MOV     TIME0_5S_count,#00H
002F D200     F      348             SETB    flag0_5s
                     349     ;       }
                     350                             ; SOURCE LINE # 54
                     351     ; }
                     352                             ; SOURCE LINE # 55
0031                 353     ?C0009:
0031 D0D0            354             POP     PSW
0033 D082            355             POP     DPL
0035 D083            356             POP     DPH
0037 D0F0            357             POP     B
0039 D0E0            358             POP     ACC
003B 32              359             RETI    
                     360     ; END OF time2
                     361     
                     362     ;  
                     363     ; main()
                     364     
----                 365             RSEG  ?PR?main?TEST_INT0
0000                 366     main:
                     367             USING   0
                     368                             ; SOURCE LINE # 57
                     369     ; {     unsigned long TMPA,P0,P1=0;
                     370                             ; SOURCE LINE # 58
0000 E4              371             CLR     A
0001 F500     F      372             MOV     P1?542+03H,A
0003 F500     F      373             MOV     P1?542+02H,A
0005 F500     F      374             MOV     P1?542+01H,A
0007 F500     F      375             MOV     P1?542,A
                     376     ;       float f,p; 
                     377     ; 
                     378     ;       TMOD=0X19;
                     379                             ; SOURCE LINE # 61
0009 758919          380             MOV     TMOD,#019H
                     381     ;       ET0=1;  
                     382                             ; SOURCE LINE # 62
000C D2A9            383             SETB    ET0
                     384     ;       EX0=1;
                     385                             ; SOURCE LINE # 63
000E D2A8            386             SETB    EX0
                     387     ;       IT0=1;
A51 MACRO ASSEMBLER  TEST_INT0                                                            03/20/2009 23:30:11 PAGE     7

                     388                             ; SOURCE LINE # 64
0010 D288            389             SETB    IT0
                     390     ;       TR0=1;  
                     391                             ; SOURCE LINE # 65
0012 D28C            392             SETB    TR0
                     393     ;       TH0=0;
                     394                             ; SOURCE LINE # 66
0014 F58C            395             MOV     TH0,A
                     396     ;       TL0=0;
                     397                             ; SOURCE LINE # 67
0016 F58A            398             MOV     TL0,A
                     399     ; 
                     400     ;       RCAP2H=0xe8;
                     401                             ; SOURCE LINE # 69
0018 75CBE8          402             MOV     RCAP2H,#0E8H
                     403     ;       RCAP2L=0xef;//T2的定时初值,用于事牍苌

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