youyuanlvbo.mdl
来自「一个MATLAB的有源滤波的电子仿真图」· MDL 代码 · 共 2,121 行 · 第 1/5 页
MDL
2,121 行
Block {
BlockType Saturate
Name "Saturation2"
Position [1655, 465, 1675, 485]
Orientation "up"
UpperLimit "1"
LowerLimit "-1"
}
Block {
BlockType Scope
Name "Scope"
Ports [3]
Position [330, 560, 365, 610]
Floating off
Location [5, 56, 1285, 773]
Open off
NumInputPorts "3"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
}
TimeRange "0.06"
YMin "-5~-5~-5"
YMax "5~5~5"
SaveToWorkspace on
SaveName "s"
DataFormat "StructureWithTime"
MaxDataPoints "500000"
SampleTime "0"
}
Block {
BlockType Scope
Name "Scope1"
Ports [3]
Position [1505, 255, 1540, 305]
Floating off
Location [5, 56, 1285, 773]
Open off
NumInputPorts "3"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
}
TimeRange "0.06"
YMin "-1~-1~-1"
YMax "1~1~1"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
MaxDataPoints "500000"
SampleTime "0"
}
Block {
BlockType Scope
Name "Scope2"
Ports [3]
Position [710, 65, 745, 115]
Floating off
Location [5, 56, 1285, 773]
Open off
NumInputPorts "3"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
}
TimeRange "0.06"
YMin "-5~-5~-5"
YMax "5~5~5"
SaveToWorkspace on
SaveName "l"
DataFormat "StructureWithTime"
MaxDataPoints "500000"
SampleTime "0"
}
Block {
BlockType Reference
Name "Series RLC Branch"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [635, 289, 680, 311]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "1.0"
Inductance "1e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Series RLC Branch1"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [635, 334, 680, 356]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "1.0"
Inductance "1e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Series RLC Branch2"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [635, 379, 680, 401]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "1.0"
Inductance "1e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Series RLC Branch3"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [906, 305, 934, 375]
Orientation "down"
NamePlacement "alternate"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "RL"
Resistance "10"
Inductance "35e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Series RLC Branch4"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [1175, 124, 1220, 146]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "1.0"
Inductance "3e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Series RLC Branch5"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [1175, 169, 1220, 191]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "1.0"
Inductance "3e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Series RLC Branch6"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [1175, 214, 1220, 236]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "1.0"
Inductance "3e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Sin
Name "Sine Wave"
Ports [0, 1]
Position [575, 695, 605, 725]
SineType "Time based"
Frequency "100*pi"
Phase "pi/2"
SampleTime "0"
}
Block {
BlockType Sin
Name "Sine Wave1"
Ports [0, 1]
Position [575, 635, 605, 665]
SineType "Time based"
Frequency "100*pi"
SampleTime "0"
}
Block {
BlockType SubSystem
Name "Subsystem"
Ports [3, 0, 0, 0, 0, 3]
Position [1560, 39, 1600, 231]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "Subsystem"
Location [2, 82, 1253, 736]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [35, 288, 65, 302]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "In2"
Position [930, 328, 960, 342]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "In3"
Position [1915, 343, 1945, 357]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "DC Voltage Source"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [775, 295, 795, 330]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/DC Voltage Sou"
"rce"
SourceType "DC Voltage Source"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Amplitude "280"
Measurements "None"
}
Block {
BlockType Reference
Name "DC Voltage Source1"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [765, 560, 785, 595]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/DC Voltage Sou"
"rce"
SourceType "DC Voltage Source"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Amplitude "280"
Measurements "None"
}
Block {
BlockType Reference
Name "DC Voltage Source10"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [2655, 350, 2675, 385]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/DC Voltage Sou"
"rce"
SourceType "DC Voltage Source"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Amplitude "280"
Measurements "None"
}
Block {
BlockType Reference
Name "DC Voltage Source11"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [2645, 615, 2665, 650]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/DC Voltage Sou"
"rce"
SourceType "DC Voltage Source"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Amplitude "280"
Measurements "None"
}
Block {
BlockType Reference
Name "DC Voltage Source12"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [2660, 885, 2680, 920]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/DC Voltage Sou"
"rce"
SourceType "DC Voltage Source"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Amplitude "280"
Measurements "None"
}
Block {
BlockType Reference
Name "DC Voltage Source13"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [2670, 1140, 2690, 1175]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/DC Voltage Sou"
"rce"
SourceType "DC Voltage Source"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
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