demo1.vhd

总体演示程序DEMO_FPGA.rar

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- 电子琴；
entity demo1 is
    Port (clk : in std_logic;
	       a,b,c,d,e,f,g,h : in std_logic;
			 tone : out std_logic);
end demo1;

architecture Behavioral of demo1 is

signal aa,bb,cc,dd,ee,ff,gg,hh : std_logic;
signal clk1m : std_logic;
signal addr : std_Logic_Vector(11 downto 0);
signal we : std_logic;
signal dout : std_Logic_vector(7 downto 0);
signal din : std_logic_vector(7 downto 0);
begin
 
process(clk)
variable c : integer range 0 to 50;
begin
   if rising_edge(clk) then
	   if c<50 then c:=c+1;
		   if c<25 then clk1m<='1';
			else clk1m<='0';
			end if;
		else c:=0;
		end if;
	end if;
end process;

tone_a : process(a,clk1m)
variable c : integer range 0 to 3802;
begin
   if a='1' then c:=0;aa<='1';
	elsif rising_edge(clk1m) then	c:=c+1;
	   if c<1900  then aa<='0';
		elsif c<3802 then aa<='1';
		else c:=0;
		end if;
   end if;
end process;

tone_b : process(b,clk1m)
variable c : integer range 0 to 3412;
begin
   if b='1' then c:=0;bb<='1';
	elsif rising_edge(clk1m) then	c:=c+1;
	   if c<1700  then bb<='0';
		elsif c<3412 then	bb<='1';
		else c:=0;
		end if;
   end if;
end process;

tone_c : process(c,clk1m)
variable ct : integer range 0 to 3039;
begin
   if c='1' then ct:=0;cc<='1';
	elsif rising_edge(clk1m) then	ct:=ct+1;
	   if ct<1500  then cc<='0';
		elsif ct<3039 then cc<='1';
		else ct:=0;
		end if;
   end if;
end process;

tone_d : process(d,clk1m)
variable c : integer range 0 to 2865;
begin
   if d='1' then c:=0;dd<='1';
	elsif rising_edge(clk1m) then	c:=c+1;
	   if c<1400  then dd<='0';
		elsif c<2865 then dd<='1';
		else c:=0;
		end if;
   end if;
end process;

tone_e : process(e,clk1m)
variable c : integer range 0 to 2551;
begin
   if  e='1' then c:=0;ee<='1';
	elsif rising_edge(clk1m) then	c:=c+1;
	   if c<1200  then ee<='0';
		elsif c<2551 then ee<='1';
		else c:=0;
		end if;
   end if;
end process;

tone_f : process(f,clk1m)
variable c : integer range 0 to 2272;
begin
   if f='1' then c:=0;ff<='1';
	elsif rising_edge(clk1m) then	c:=c+1;
	   if c<1100  then ff<='0';
		elsif c<2272 then ff<='1';
		else c:=0;
		end if;
   end if;
end process;

tone_g : process(g,clk1m)
variable c : integer range 0 to 2028;
begin
   if g='1' then c:=0;gg<='1';
	elsif rising_edge(clk1m) then	c:=c+1;
	   if c<1000  then gg<='0';
		elsif c<2028 then gg<='1';
		else c:=0;
		end if;
   end if;
end process;

tone_h : process(h,clk1m)
variable c : integer range 0 to 1901;
begin
   if h='1' then c:=0;hh<='1';
	elsif rising_edge(clk1m) then	c:=c+1;
	   if c<999  then hh<='0';
		elsif c<1901 then hh<='1';
		else c:=0;
		end if;
   end if;
end process;
  
  tone<=aa and bb and cc and dd and ee and ff and gg and hh;

end Behavioral;