mode_clk.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    01:18:34 03/25/05
-- Design Name:    
-- Module Name:    mode_clk - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mode_clk is
    Port ( clk : in std_logic;
           ireset : in std_logic;
           en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           dout : out std_logic_vector(7 downto 0));
end mode_clk;

architecture Behavioral of mode_clk is
component page1 
    Port ( en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           oh : in std_logic_vector(7 downto 0);
           om : in std_logic_vector(7 downto 0);
           os : in std_logic_vector(7 downto 0);
           dout : out std_logic_vector(7 downto 0));
end component;

component digital_clk 
    Port ( clk : in std_logic;
           ireset : in std_logic;
           oh : out std_logic_vector(7 downto 0);
           om : out std_logic_vector(7 downto 0);
           os : out std_logic_vector(7 downto 0));
end component ;

signal oh,om,os : std_logic_vector(7 downto 0);

begin
u0: digital_clk port map( 
           clk=>clk,
           ireset=>ireset,
           oh=>oh,
           om=>om,
           os=>os);

u1: page1 port map( 
           en=>en,
		 addr=>addr,
		 din=>din,
           oh=>oh,
           om=>om,
           os=>os,
		 dout=>dout);

end Behavioral;