coregen.cgp

来自「总体演示程序DEMO_FPGA.rar」· CGP 代码 · 共 22 行

SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = e:\demo_fpga\tmp
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = e:\demo_fpga\
SET device = xc2s100e
# SET projectname = coregen
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = pq208
SET createndf = False
SET designentry = VHDL
SET devicefamily = Spartan2
SET formalverification = False
SET removerpms = False