mode_clk.syr

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.93 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.94 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: mode_clk.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "mode_clk.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "mode_clk"
Output Format                      : NGC
Target Device                      : xc2s100e-6-pq208

---- Source Options
Top Module Name                    : mode_clk
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : mode_clk.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/DEMO_FPGA/digital_clk.vhd" in Library work.
Entity <digital_clk> compiled.
Entity <digital_clk> (Architecture <behavioral>) compiled.
Compiling vhdl file "E:/DEMO_FPGA/page_dclk.vhd" in Library work.
Architecture digital_clock of Entity page1 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mode_clk.vhd" in Library work.
Architecture behavioral of Entity mode_clk is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mode_clk> (Architecture <behavioral>).
Entity <mode_clk> analyzed. Unit <mode_clk> generated.

Analyzing Entity <digital_clk> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <$n0006> in unit <digital_clk> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <$n0007> in unit <digital_clk> never changes during circuit operation. The register is replaced by logic.
Entity <digital_clk> analyzed. Unit <digital_clk> generated.

Analyzing Entity <page1> (Architecture <digital_clock>).
Entity <page1> analyzed. Unit <page1> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <page1>.
    Related source file is "E:/DEMO_FPGA/page_dclk.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
Unit <page1> synthesized.


Synthesizing Unit <digital_clk>.
    Related source file is "E:/DEMO_FPGA/digital_clk.vhd".
    Found 4-bit adder for signal <$n0000> created at line 60.
    Found 4-bit adder for signal <$n0001> created at line 62.
    Found 8-bit register for signal <c1>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <digital_clk> synthesized.


Synthesizing Unit <mode_clk>.
    Related source file is "E:/DEMO_FPGA/mode_clk.vhd".
Unit <mode_clk> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 4-bit adder                       : 2
# Registers                        : 8
 1-bit register                    : 8
# Latches                          : 1
 8-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mode_clk> ...

Optimizing unit <page1> ...

Optimizing unit <digital_clk> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mode_clk, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : mode_clk.ngr
Top Level Output File Name         : mode_clk
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 28

Macro Statistics :
# Registers                        : 8
#      1-bit register              : 8
# Adders/Subtractors               : 2
#      4-bit adder                 : 2

Cell Usage :
# BELS                             : 32
#      INV                         : 2
#      LUT2                        : 6
#      LUT2_L                      : 1
#      LUT3                        : 2
#      LUT3_L                      : 2
#      LUT4                        : 14
#      LUT4_L                      : 3
#      MUXF5                       : 2
# FlipFlops/Latches                : 16
#      FDC                         : 2
#      FDCE                        : 4
#      FDP                         : 2
#      LD                          : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 27
#      IBUF                        : 19
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                      16  out of   1200     1%  
 Number of Slice Flip Flops:            16  out of   2400     0%  
 Number of 4 input LUTs:                28  out of   2400     1%  
 Number of bonded IOBs:                 28  out of    146    19%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 8     |
u1/_n0001(u1/_n00012:O)            | NONE(*)(u1/dout_6)     | 8     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.517ns (Maximum Frequency: 181.258MHz)
   Minimum input arrival time before clock: 7.315ns
   Maximum output required time after clock: 6.613ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.517ns (frequency: 181.258MHz)
  Total number of paths / destination ports: 38 / 12
-------------------------------------------------------------------------
Delay:               5.517ns (Levels of Logic = 1)
  Source:            u0/c1_0 (FF)
  Destination:       u0/c1_5 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u0/c1_0 to u0/c1_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              6   0.992   1.850  u0/c1_0 (u0/c1_0)
     LUT4:I0->O            4   0.468   1.520  u0/_n00121 (u0/_n0012)
     FDCE:CE                   0.687          u0/c1_4
    ----------------------------------------
    Total                      5.517ns (2.147ns logic, 3.370ns route)
                                       (38.9% logic, 61.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'u1/_n00012:O'
  Total number of paths / destination ports: 70 / 8
-------------------------------------------------------------------------
Offset:              7.315ns (Levels of Logic = 4)
  Source:            addr<1> (PAD)
  Destination:       u1/dout_5 (LATCH)
  Destination Clock: u1/_n00012:O falling

  Data Path: addr<1> to u1/dout_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             7   0.797   1.950  addr_1_IBUF (addr_1_IBUF)
     LUT2:I0->O            1   0.468   0.920  u1/Ker6_SW0 (N4)
     LUT4:I3->O            4   0.468   1.520  u1/Ker6 (u1/N6)
     LUT2:I1->O            1   0.468   0.000  u1/_n0002<4>1 (u1/_n0002<4>)
     LD:D                      0.724          u1/dout_4
    ----------------------------------------
    Total                      7.315ns (2.925ns logic, 4.390ns route)
                                       (40.0% logic, 60.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1/_n00012:O'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              6.613ns (Levels of Logic = 1)
  Source:            u1/dout_7 (LATCH)
  Destination:       dout<7> (PAD)
  Source Clock:      u1/_n00012:O falling

  Data Path: u1/dout_7 to dout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.091   0.920  u1/dout_7 (u1/dout_7)
     OBUF:I->O                 4.602          dout_7_OBUF (dout<7>)
    ----------------------------------------
    Total                      6.613ns (5.693ns logic, 0.920ns route)
                                       (86.1% logic, 13.9% route)

=========================================================================
CPU : 12.43 / 13.52 s | Elapsed : 12.00 / 13.00 s
 
--> 

Total memory usage is 88484 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    3 (   0 filtered)