top_mode_cymometer.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    03:54:34 03/25/05
-- Design Name:    
-- Module Name:    top_mode_cymometer - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_mode_cymometer is
    Port ( clka,clkb : std_logic;
           tclk : std_logic;
           en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           dout : out std_logic_vector(7 downto 0));

end top_mode_cymometer;

architecture Behavioral of top_mode_cymometer is
component page4
    Port ( en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           dint : in std_logic_vector(23 downto 0);
           dout : out std_logic_vector(7 downto 0));
end component;

component mode_cymometer 
    Port ( clka : in std_logic;
           clkb : in std_logic;
           tclk : in std_logic;
           dout : out std_logic_vector(23 downto 0));
end component;

signal dt : std_logic_vector(23 downto 0);

begin
u0 : page4 port map(
           en=>en,
		 addr=>addr,
		 din=>din,
		 dint=>dt,
		 dout=>dout);

u1 : mode_cymometer port map(
           clka=>clka,
		 clkb=>clkb,
		 tclk=>tclk,
		 dout=>dt);

end Behavioral;