dfgf.ant

总体演示程序DEMO_FPGA.rar

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1.01i
--  \   \         Application : ISE Foundation
--  /   /         Filename : dfgf.ant
-- /___/   /\     Timestamp : Fri Mar 25 03:08:13 2005
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: dfgf
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY dfgf IS
END dfgf;

ARCHITECTURE testbench_arch OF dfgf IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "E:\DEMO_FPGA\dfgf.ano";

    COMPONENT digital_clk
        PORT (
            clk : In std_logic;
            ireset : In std_logic;
            oh : Out std_logic_vector (7 DownTo 0);
            om : Out std_logic_vector (7 DownTo 0);
            os : Out std_logic_vector (7 DownTo 0)
        );
    END COMPONENT;

    SIGNAL clk : std_logic := '0';
    SIGNAL ireset : std_logic := '1';
    SIGNAL oh : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL om : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL os : std_logic_vector (7 DownTo 0) := "00000000";

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 20 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : digital_clk
        PORT MAP (
            clk => clk,
            ireset => ireset,
            oh => oh,
            om => om,
            os => os
        );

        PROCESS    -- clock process for clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Annotation process for clk
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_oh(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", oh, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oh);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_om(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", om, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, om);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_os(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", os, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, os);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_oh(0);
            ANNOTATE_om(0);
            ANNOTATE_os(0);
            WAIT for OFFSET;
            TX_TIME := TX_TIME + 0;
            ANNO_LOOP : LOOP
                --Rising Edge
                WAIT for 11 ns;
                TX_TIME := TX_TIME + 11;
                ANNOTATE_oh(TX_TIME);
                ANNOTATE_om(TX_TIME);
                ANNOTATE_os(TX_TIME);
                WAIT for 9 ns;
                TX_TIME := TX_TIME + 9;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  9ns
                WAIT FOR 9 ns;
                ireset <= '0';
                -- -------------------------------------
                WAIT FOR 1011 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;