demo_all.mrp

总体演示程序DEMO_FPGA.rar

Release 7.1.01i Map H.39
Xilinx Mapping Report File for Design 'demo_all'

Design Information
------------------
Command Line   : E:/Program/EDA/Xilinx/bin/nt/map.exe -ise
e:\demo_fpga\DEMO_FPGA.ise -intstyle ise -p xc2s100e-pq208-6 -cm area -pr b -k 4
-c 100 -tx off -o demo_all_map.ncd demo_all.ngd demo_all.pcf 
Target Device  : xc2s100e
Target Package : pq208
Target Speed   : -6
Mapper Version : spartan2e -- $Revision: 1.26.6.4 $
Mapped Date    : Sun Apr 03 23:21:03 2005

Design Summary
--------------
Number of errors:      0
Number of warnings:   15
Logic Utilization:
  Total Number Slice Registers:     720 out of  2,400   30%
    Number used as Flip Flops:                    666
    Number used as Latches:                        54
  Number of 4 input LUTs:         1,238 out of  2,400   51%
Logic Distribution:
    Number of occupied Slices:                       1,032 out of  1,200   86%
    Number of Slices containing only related logic:  1,032 out of  1,032  100%
    Number of Slices containing unrelated logic:         0 out of  1,032    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,781 out of  2,400   74%
      Number used as logic:                     1,238
      Number used as a route-thru:                543
   Number of bonded IOBs:            46 out of    142   32%
      IOB Flip Flops:                               3
      IOB Latches:                                 23
   Number of Block RAMs:              3 out of     10   30%
   Number of GCLKs:                   4 out of      4  100%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  66,571
Additional JTAG gate count for IOBs:  2,256
Peak Memory Usage:  112 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol
   "u4/clk1k_BUFG" (output signal=u4/clk1k) has a mix of clock and non-clock
   loads. The non-clock loads are:
   Pin I2 of u4/reg_clk1k1
   Pin I3 of u4/u5/u1/_n00281
WARNING:PhysDesignRules:372 - Gated clock. Clock net u1/u3/PreCLK is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u1/u2/_n0003 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u3/button is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u4/u5/u0/_n0001 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u4/u8/_n0001 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0124 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0002 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u2/button is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0123 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u1/u1/_n0002 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u4/u4/u1/_n0001 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0003 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0125 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0122 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   4 block(s) removed
   8 block(s) optimized away
   4 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "u4/u7/datain_0_rt" is unused and has been removed.
 Unused block "u4/u7/datain_0_rt" (ROM) removed.
The signal "u4/u7/Mmult__n0030_inst_lut2_28_rt" is unused and has been removed.