12mhz_generator.vhd

总体演示程序DEMO_FPGA.rar

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MHz_generator is
    Port ( clk : in std_logic;
           clk_12MHz : out std_logic;
			  clk_8Hz   : out std_logic);
end MHz_generator;

architecture Behavioral of MHz_generator is

begin
    process(clk)
	 variable n12,n8:integer:=0;
	 begin
	    if rising_edge(clk)then
		    n12:=n12+1;
			 n8:=n8+1;
			 if n12<=1   then
			    clk_12MHz<='1';
			 else
			    clk_12MHz<='0';
			 end if;
			 if n8<= 4000000   then
			    clk_8Hz<='1';
			 else
			    clk_8Hz<='0';
			 end if;
			 if n12= 3   then
			    n12:=0;
			 end if;
			 if n8= 8000000    then
			    n8:=0;
			 end if;
		 end if;
	  end process;


end Behavioral;