core.tpl

总体演示程序DEMO_FPGA.rar

[COREGEN.VERILOG Component Instantiation.mem_infor]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mem_infor YourInstanceName ("
text007="    .addr(addr),"
text008="    .clk(clk),"
text009="    .dout(dout));"
text010=""
text011=" "
type=template
[COREGEN.VHDL Component Instantiation.mem_infor]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mem_infor"
text005="    port ("
text006="    addr: IN std_logic_VECTOR(9 downto 0);"
text007="    clk: IN std_logic;"
text008="    dout: OUT std_logic_VECTOR(7 downto 0));"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : mem_infor"
text020="        port map ("
text021="            addr => addr,"
text022="            clk => clk,"
text023="            dout => dout);"
text024=" "
type=template