digital_clk.cmd_log

总体演示程序DEMO_FPGA.rar

xst -intstyle ise -ifn __projnav/digital_clk.xst -ofn digital_clk.syr
xst -intstyle ise -ifn __projnav/digital_clk.xst -ofn digital_clk.syr
xst -intstyle ise -ifn __projnav/digital_clk.xst -ofn digital_clk.syr
ngdbuild -intstyle ise -dd "e:\demo_fpga/_ngo" -nt timestamp -i  -p xc2s100e-pq208-6 digital_clk.ngc digital_clk.ngd
map -intstyle ise -p xc2s100e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o digital_clk_map.ncd digital_clk.ngd digital_clk.pcf
par -w -intstyle ise -ol std -t 1 digital_clk_map.ncd digital_clk.ncd digital_clk.pcf
trce -intstyle ise -e 3 -l 3 -s 6 -xml digital_clk digital_clk.ncd -o digital_clk.twr digital_clk.pcf
netgen -intstyle ise -s 6   -pcf digital_clk.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim digital_clk.ncd digital_clk_timesim.vhd
xst -intstyle ise -ifn __projnav/digital_clk.xst -ofn digital_clk.syr
ngdbuild -intstyle ise -dd "e:\demo_fpga/_ngo" -nt timestamp -i  -p xc2s100e-pq208-6 digital_clk.ngc digital_clk.ngd
map -intstyle ise -p xc2s100e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o digital_clk_map.ncd digital_clk.ngd digital_clk.pcf
par -w -intstyle ise -ol std -t 1 digital_clk_map.ncd digital_clk.ncd digital_clk.pcf
trce -intstyle ise -e 3 -l 3 -s 6 -xml digital_clk digital_clk.ncd -o digital_clk.twr digital_clk.pcf
netgen -intstyle ise -s 6   -pcf digital_clk.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim digital_clk.ncd digital_clk_timesim.vhd