__projnav.log

总体演示程序DEMO_FPGA.rar

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 3 secs 

Writing design to file top_fpga_demo.ncd


Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 3 secs 

Starting Router

Phase 1: 1780 unrouted;       REAL time: 4 secs 

Phase 2: 1622 unrouted;       REAL time: 12 secs 

Phase 3: 446 unrouted;       REAL time: 14 secs 

Phase 4: 0 unrouted;       REAL time: 14 secs 

Total REAL time to Router completion: 14 secs 
Total CPU time to Router completion: 12 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|               clk1k |      GCLKBUF1| No   |   68 |  0.279     |  0.542      |
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      GCLKBUF0| No   |   43 |  0.053     |  0.409      |
+---------------------+--------------+------+------+------------+-------------+
|         u4/u0/sclkb |         Local|      |    6 |  0.114     |  3.453      |
+---------------------+--------------+------+------+------------+-------------+
|         u4/u0/sclka |         Local|      |    5 |  2.127     |  3.659      |
+---------------------+--------------+------+------+------------+-------------+
|        u5/u0/_n0001 |         Local|      |    7 |  0.144     |  3.614      |
+---------------------+--------------+------+------+------------+-------------+
|        u4/u1/_n0001 |         Local|      |    6 |  0.041     |  3.547      |
+---------------------+--------------+------+------+------------+-------------+
|                clk1 |         Local|      |    6 |  0.055     |  3.423      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 16 secs 
Total CPU time to PAR completion: 13 secs 

Peak Memory Usage:  76 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file top_fpga_demo.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "top_fpga_demo" is an NCD, version 3.1, device xc2s100e, package pq208, speed
-6

Analysis completed Fri Mar 25 05:27:04 2005
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 3 secs 







Started process "Generate Programming File".

WARNING:PhysDesignRules:372 - Gated clock. Clock net u5/u0/_n0001 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u4/u1/_n0001 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\demo_fpga/_ngo -nt timestamp -uc
dfddf.ucf -p xc2s100e-pq208-6 electronic_organ.ngc electronic_organ.ngd 

Reading NGO file 'E:/DEMO_FPGA/electronic_organ.ngc' ...

Applying constraints in "dfddf.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "electronic_organ.ngd" ...

Writing NGDBUILD log file "electronic_organ.bld"...

NGDBUILD done.




Started process "Map".

Using target part "2s100epq208-6".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:            10 out of  2,400    1%
Logic Distribution:
    Number of occupied Slices:                           6 out of  1,200    1%
    Number of Slices containing only related logic:      6 out of      6  100%
    Number of Slices containing unrelated logic:         0 out of      6    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        10 out of  2,400    1%
   Number of bonded IOBs:             5 out of    142    3%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  92
Additional JTAG gate count for IOBs:  288
Peak Memory Usage:  97 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "electronic_organ_map.mrp" for details.




Started process "Place & Route".




Constraints file: electronic_organ.pcf.
Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "electronic_organ" is an NCD, version 3.1, device xc2s100e, package pq208,
speed -6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)


Device speed data version:  "PRODUCTION 1.18 2005-01-22".


Device Utilization Summary:

   Number of GCLKs                     1 out of 4      25%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs             5 out of 142     3%
      Number of LOCed IOBs             5 out of 5     100%

   Number of SLICEs                    6 out of 1200    1%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896b6) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
.
Phase 6.8 (Checksum:98b353) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file electronic_organ.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 45 unrouted;       REAL time: 2 secs 

Phase 2: 44 unrouted;       REAL time: 2 secs 

Phase 3: 12 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      GCLKBUF0| No   |    1 |  0.000     |  0.537      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  64 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file electronic_organ.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "electronic_organ" is an NCD, version 3.1, device xc2s100e, package pq208,
speed -6

Analysis completed Fri Mar 25 05:32:29 2005
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


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