__projnav.log

总体演示程序DEMO_FPGA.rar

	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <lcd> synthesized.


Synthesizing Unit <page_information>.
    Related source file is "E:/DEMO_FPGA/mem_inform.vhd".
Unit <page_information> synthesized.


Synthesizing Unit <top_fpga_demo>.
    Related source file is "E:/DEMO_FPGA/Top_FPGA_demo.vhd".
    Found 10-bit comparator less for signal <$n0004> created at line 156.
    Found 10-bit comparator less for signal <$n0005> created at line 156.
    Found 16-bit comparator less for signal <$n0006> created at line 145.
    Found 16-bit comparator less for signal <$n0007> created at line 145.
    Found 10-bit adder for signal <$n0010> created at line 155.
    Found 16-bit adder for signal <$n0011> created at line 144.
    Found 1-bit register for signal <clk1>.
    Found 1-bit register for signal <clk1k>.
    Found 16-bit up counter for signal <cnt>.
    Found 10-bit up counter for signal <cnt0>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <top_fpga_demo> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <current_state[1:8]> with speed1 encoding.
--------------------------------
 State              | Encoding
--------------------------------
 set_dlnf           | 10000000
 clear_lcd          | 01000000
 set_cursor         | 00100000
 set_location3      | 00000001
 write_data2        | 00010000
 set_dcb            | 00001000
 set_location       | 00000100
 write_data         | 00000010
 write_data3        | unreached
 set_location2      | unreached
 set_cgram_location | unreached
 write_cgram        | unreached
--------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <current_state[1:4]> with gray encoding.
-------------------
 State | Encoding
-------------------
 st0   | 0000
 st1   | 0010
 st2   | 0110
 st3   | 0011
 st4   | 0111
 st5   | 0001
 st6   | 0101
 st7   | 0100
 st8   | 1100
 st9   | 1101
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# Adders/Subtractors               : 21
 10-bit adder                      : 1
 16-bit adder                      : 1
 4-bit adder                       : 11
 5-bit adder                       : 2
 5-bit subtractor                  : 1
 8-bit adder                       : 5
# Counters                         : 3
 10-bit up counter                 : 1
 16-bit up counter                 : 1
 4-bit up counter                  : 1
# Registers                        : 46
 1-bit register                    : 26
 24-bit register                   : 1
 4-bit register                    : 11
 5-bit register                    : 2
 8-bit register                    : 6
# Latches                          : 2
 8-bit latch                       : 2
# Comparators                      : 19
 10-bit comparator less            : 2
 16-bit comparator less            : 2
 18-bit comparator greater         : 2
 4-bit comparator less             : 6
 5-bit comparator greater          : 1
 5-bit comparator less             : 1
 8-bit comparator less             : 5
# Multiplexers                     : 7
 4-bit 4-to-1 multiplexer          : 7

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Reading module "mem_infor.ngo" ( "mem_infor.ngo" unchanged since last run )...
Loading core <mem_infor> for timing and area information for instance <U0>.

Optimizing unit <top_fpga_demo> ...

Optimizing unit <page1> ...

Optimizing unit <page4> ...

Optimizing unit <button1> ...

Optimizing unit <mode_cymometer> ...

Optimizing unit <digital_clk> ...
WARNING:Xst:1710 - FF/Latch  <d_3> (without init value) has a constant value of 0 in block <digital_clk>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <d0_3> (without init value) has a constant value of 0 in block <digital_clk>.

Optimizing unit <lcd> ...

Optimizing unit <page_step> ...

Optimizing unit <electronic_organ> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_fpga_demo, actual ratio is 24.
FlipFlop u3/c_0 has been replicated 1 time(s)
FlipFlop u3/c_2 has been replicated 1 time(s)
FlipFlop u3/c_3 has been replicated 1 time(s)
FlipFlop u3/c_4 has been replicated 1 time(s)
FlipFlop clk1 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                     272  out of   1200    22%  
 Number of Slice Flip Flops:           202  out of   2400     8%  
 Number of 4 input LUTs:               442  out of   2400    18%  
 Number of bonded IOBs:                 24  out of    146    16%  
 Number of BRAMs:                        2  out of     10    20%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk1k:Q                            | BUFG                   | 95    |
u4/u1/_n0001(u4/u1/_n00012:O)      | NONE(*)(u4/u1/dout_2)  | 8     |
clk                                | BUFGP                  | 68    |
u5/u0/_n0001(u5/u0/_n00012:O)      | NONE(*)(u5/u0/dout_4)  | 8     |
clk1:Q                             | NONE                   | 9     |
u4/u0/sclkb:Q                      | NONE                   | 8     |
u4/u0/sclka:Q                      | NONE                   | 8     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 20.616ns (Maximum Frequency: 48.506MHz)
   Minimum input arrival time before clock: 8.766ns
   Maximum output required time after clock: 11.964ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\demo_fpga/_ngo -nt timestamp -uc
top_fpga.ucf -p xc2s100e-pq208-6 top_fpga_demo.ngc top_fpga_demo.ngd 

Reading NGO file 'E:/DEMO_FPGA/top_fpga_demo.ngc' ...
Reading module "mem_infor.ngo" ( "mem_infor.ngo" unchanged since last run )...
Loading design module "e:\demo_fpga\_ngo\mem_infor.ngo"...

Applying constraints in "top_fpga.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "top_fpga_demo.ngd" ...

Writing NGDBUILD log file "top_fpga_demo.bld"...

NGDBUILD done.




Started process "Map".

Using target part "2s100epq208-6".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Total Number Slice Registers:     201 out of  2,400    8%
    Number used as Flip Flops:                    185
    Number used as Latches:                        16
  Number of 4 input LUTs:           361 out of  2,400   15%
Logic Distribution:
    Number of occupied Slices:                         266 out of  1,200   22%
    Number of Slices containing only related logic:    266 out of    266  100%
    Number of Slices containing unrelated logic:         0 out of    266    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          463 out of  2,400   19%
      Number used as logic:                       361
      Number used as a route-thru:                102
   Number of bonded IOBs:            23 out of    142   16%
      IOB Flip Flops:                               1
   Number of Block RAMs:              2 out of     10   20%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  37,174
Additional JTAG gate count for IOBs:  1,152
Peak Memory Usage:  100 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "top_fpga_demo_map.mrp" for details.




Started process "Place & Route".




Constraints file: top_fpga_demo.pcf.
Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "top_fpga_demo" is an NCD, version 3.1, device xc2s100e, package pq208, speed
-6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)


Device speed data version:  "PRODUCTION 1.18 2005-01-22".


Device Utilization Summary:

   Number of BLOCKRAMs                 2 out of 10     20%
   Number of GCLKs                     2 out of 4      50%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs            23 out of 142    16%
      Number of LOCed IOBs            23 out of 23    100%

   Number of SLICEs                  266 out of 1200   22%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989fe9) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
...................
Phase 6.8 (Checksum:9f6cb1) REAL time: 3 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs