__projnav.log

总体演示程序DEMO_FPGA.rar

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk100:Q                           | BUFG                   | 50    |
clk1k:Q                            | BUFG                   | 57    |
clk1m:Q                            | NONE                   | 11    |
clk                                | BUFGP                  | 7     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 13.008ns (Maximum Frequency: 76.876MHz)
   Minimum input arrival time before clock: 2.441ns
   Maximum output required time after clock: 10.254ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3498 - No primary, secondary unit in the file "E:/DEMO_FPGA/mem_infor.vhd. Ignore this file from project file "top_fpga_demo_vhdl.prj".
Compiling vhdl file "E:/DEMO_FPGA/page4.vhd" in Library work.
Architecture behavioral of Entity page4 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mode_cymometer.vhd" in Library work.
Architecture behavioral of Entity mode_cymometer is up to date.
Compiling vhdl file "E:/DEMO_FPGA/digital_clk.vhd" in Library work.
Architecture behavioral of Entity digital_clk is up to date.
Compiling vhdl file "E:/DEMO_FPGA/page_dclk.vhd" in Library work.
Architecture digital_clock of Entity page1 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/button1.vhd" in Library work.
Architecture keyboards of Entity button1 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mem_inform.vhd" in Library work.
Architecture data of Entity page_information is up to date.
Compiling vhdl file "E:/DEMO_FPGA/lcd_driver.vhd" in Library work.
Architecture driver of Entity lcd is up to date.
Compiling vhdl file "E:/DEMO_FPGA/keyboards.vhd" in Library work.
Architecture behavioral of Entity keyboards is up to date.
Compiling vhdl file "E:/DEMO_FPGA/page_step.vhd" in Library work.
Architecture behavioral of Entity page_step is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mode_clk.vhd" in Library work.
Architecture behavioral of Entity mode_clk is up to date.
Compiling vhdl file "E:/DEMO_FPGA/top_mode_cymometer.vhd" in Library work.
Architecture behavioral of Entity top_mode_cymometer is up to date.
Compiling vhdl file "E:/DEMO_FPGA/electronic_organ.vhd" in Library work.
Architecture behavioral of Entity electronic_organ is up to date.
Compiling vhdl file "E:/DEMO_FPGA/Top_FPGA_demo.vhd" in Library work.
Entity <top_fpga_demo> compiled.
ERROR:HDLParsers:3312 - "E:/DEMO_FPGA/Top_FPGA_demo.vhd" Line 234. Undefined symbol 'reg_tone'.
ERROR:HDLParsers:1209 - "E:/DEMO_FPGA/Top_FPGA_demo.vhd" Line 234. reg_tone: Undefined symbol (last report in this block)
--> 

Total memory usage is 77820 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3498 - No primary, secondary unit in the file "E:/DEMO_FPGA/mem_infor.vhd. Ignore this file from project file "top_fpga_demo_vhdl.prj".
Compiling vhdl file "E:/DEMO_FPGA/page4.vhd" in Library work.
Architecture behavioral of Entity page4 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mode_cymometer.vhd" in Library work.
Architecture behavioral of Entity mode_cymometer is up to date.
Compiling vhdl file "E:/DEMO_FPGA/digital_clk.vhd" in Library work.
Architecture behavioral of Entity digital_clk is up to date.
Compiling vhdl file "E:/DEMO_FPGA/page_dclk.vhd" in Library work.
Architecture digital_clock of Entity page1 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/button1.vhd" in Library work.
Architecture keyboards of Entity button1 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mem_inform.vhd" in Library work.
Architecture data of Entity page_information is up to date.
Compiling vhdl file "E:/DEMO_FPGA/lcd_driver.vhd" in Library work.
Architecture driver of Entity lcd is up to date.
Compiling vhdl file "E:/DEMO_FPGA/keyboards.vhd" in Library work.
Architecture behavioral of Entity keyboards is up to date.
Compiling vhdl file "E:/DEMO_FPGA/page_step.vhd" in Library work.
Architecture behavioral of Entity page_step is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mode_clk.vhd" in Library work.
Architecture behavioral of Entity mode_clk is up to date.
Compiling vhdl file "E:/DEMO_FPGA/top_mode_cymometer.vhd" in Library work.
Architecture behavioral of Entity top_mode_cymometer is up to date.
Compiling vhdl file "E:/DEMO_FPGA/electronic_organ.vhd" in Library work.
Architecture behavioral of Entity electronic_organ is up to date.
Compiling vhdl file "E:/DEMO_FPGA/Top_FPGA_demo.vhd" in Library work.
Entity <top_fpga_demo> compiled.
Entity <top_fpga_demo> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_fpga_demo> (Architecture <behavioral>).
Entity <top_fpga_demo> analyzed. Unit <top_fpga_demo> generated.

Analyzing Entity <page_information> (Architecture <data>).
WARNING:Xst:766 - "E:/DEMO_FPGA/mem_inform.vhd" line 41: Generating a Black Box for component <mem_infor>.
Entity <page_information> analyzed. Unit <page_information> generated.

Analyzing Entity <lcd> (Architecture <driver>).
Entity <lcd> analyzed. Unit <lcd> generated.

Analyzing Entity <keyboards> (Architecture <behavioral>).
Entity <keyboards> analyzed. Unit <keyboards> generated.

Analyzing Entity <button1> (Architecture <keyboards>).
Entity <button1> analyzed. Unit <button1> generated.

Analyzing Entity <page_step> (Architecture <behavioral>).
Entity <page_step> analyzed. Unit <page_step> generated.

Analyzing Entity <mode_clk> (Architecture <behavioral>).
Entity <mode_clk> analyzed. Unit <mode_clk> generated.

Analyzing Entity <digital_clk> (Architecture <behavioral>).
Entity <digital_clk> analyzed. Unit <digital_clk> generated.

Analyzing Entity <page1> (Architecture <digital_clock>).
Entity <page1> analyzed. Unit <page1> generated.

Analyzing Entity <top_mode_cymometer> (Architecture <behavioral>).
WARNING:Xst:752 - "E:/DEMO_FPGA/top_mode_cymometer.vhd" line 66: Unconnected input port 'ireset' of component 'mode_cymometer' is tied to default value.
Entity <top_mode_cymometer> analyzed. Unit <top_mode_cymometer> generated.

Analyzing Entity <page4> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/DEMO_FPGA/page4.vhd" line 42: The following signals are missing in the process sensitivity list:
   dint<23>, dint<22>, dint<21>, dint<20>, dint<19>, dint<18>, dint<17>, dint<16>, dint<15>, dint<14>, dint<13>, dint<12>, dint<11>, dint<10>, dint<9>, dint<8>, dint<7>, dint<6>, dint<5>, dint<4>, dint<3>, dint<2>, dint<1>, dint<0>.
Entity <page4> analyzed. Unit <page4> generated.

Analyzing Entity <mode_cymometer> (Architecture <behavioral>).
Entity <mode_cymometer> analyzed. Unit <mode_cymometer> generated.

Analyzing Entity <electronic_organ> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <cnt> in unit <electronic_organ> never changes during circuit operation. The register is replaced by logic.
Entity <electronic_organ> analyzed. Unit <electronic_organ> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mode_cymometer>.
    Related source file is "E:/DEMO_FPGA/mode_cymometer.vhd".
WARNING:Xst:1780 - Signal <current_state> is never used or assigned.
    Found 24-bit register for signal <dout>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0015>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0016>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0017>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0018>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0019>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0020>.
    Found 4-bit adder for signal <$n0022> created at line 79.
    Found 4-bit adder for signal <$n0023> created at line 78.
    Found 4-bit adder for signal <$n0024> created at line 77.
    Found 4-bit adder for signal <$n0025> created at line 76.
    Found 4-bit adder for signal <$n0026> created at line 75.
    Found 4-bit adder for signal <$n0027> created at line 74.
    Found 4-bit register for signal <cnt1>.
    Found 4-bit register for signal <cnt2>.
    Found 4-bit register for signal <cnt3>.
    Found 4-bit register for signal <cnt4>.
    Found 4-bit register for signal <cnt5>.
    Found 4-bit register for signal <cnt6>.
    Found 1-bit register for signal <kd>.
    Found 1-bit register for signal <ris_a>.
    Found 1-bit register for signal <ris_b>.
    Summary:
	inferred  51 D-type flip-flop(s).
	inferred   6 Adder/Subtractor(s).
	inferred  24 Multiplexer(s).
Unit <mode_cymometer> synthesized.


Synthesizing Unit <page4>.
    Related source file is "E:/DEMO_FPGA/page4.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
Unit <page4> synthesized.


Synthesizing Unit <page1>.
    Related source file is "E:/DEMO_FPGA/page_dclk.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
Unit <page1> synthesized.


Synthesizing Unit <digital_clk>.
    Related source file is "E:/DEMO_FPGA/digital_clk.vhd".
    Found 4-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit adder for signal <$n0022>.
    Found 4-bit adder for signal <$n0023> created at line 48.
    Found 4-bit adder for signal <$n0024> created at line 50.
    Found 4-bit adder for signal <$n0025> created at line 64.
    Found 4-bit adder for signal <$n0026> created at line 66.
    Found 4-bit comparator less for signal <$n0027> created at line 48.
    Found 4-bit comparator less for signal <$n0028> created at line 50.
    Found 4-bit comparator less for signal <$n0029> created at line 66.
    Found 4-bit comparator less for signal <$n0030> created at line 64.
    Found 4-bit comparator less for signal <$n0032> created at line 81.
    Found 4-bit comparator less for signal <$n0033> created at line 82.
    Found 4-bit register for signal <c>.
    Found 4-bit register for signal <c0>.
    Found 4-bit up counter for signal <c1>.
    Found 4-bit register for signal <d>.
    Found 4-bit register for signal <d0>.
    Found 4-bit register for signal <d1>.
    Found 1-bit register for signal <sclka>.
    Found 1-bit register for signal <sclkb>.
    Summary:
	inferred   1 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred   6 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <digital_clk> synthesized.


Synthesizing Unit <button1>.
    Related source file is "E:/DEMO_FPGA/button1.vhd".
    Found 8-bit adder for signal <$n0002> created at line 44.
    Found 8-bit comparator less for signal <$n0003> created at line 44.
    Found 8-bit register for signal <delay>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <button1> synthesized.


Synthesizing Unit <electronic_organ>.
    Related source file is "E:/DEMO_FPGA/electronic_organ.vhd".
    Found 1-bit register for signal <tone>.
    Found 18-bit comparator greater for signal <$n0003> created at line 53.
    Found 18-bit comparator greater for signal <$n0010> created at line 53.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <electronic_organ> synthesized.


Synthesizing Unit <top_mode_cymometer>.
    Related source file is "E:/DEMO_FPGA/top_mode_cymometer.vhd".
Unit <top_mode_cymometer> synthesized.


Synthesizing Unit <mode_clk>.
    Related source file is "E:/DEMO_FPGA/mode_clk.vhd".
Unit <mode_clk> synthesized.


Synthesizing Unit <page_step>.
    Related source file is "E:/DEMO_FPGA/page_step.vhd".
    Found finite state machine <FSM_0> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 19                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | ireset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | st0                                            |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit adder for signal <$n0000> created at line 67.
    Found 5-bit subtractor for signal <$n0001> created at line 77.
    Found 5-bit comparator less for signal <$n0012> created at line 67.
    Found 5-bit comparator greater for signal <$n0013> created at line 77.
    Found 5-bit register for signal <c>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   5 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <page_step> synthesized.


Synthesizing Unit <keyboards>.
    Related source file is "E:/DEMO_FPGA/keyboards.vhd".
Unit <keyboards> synthesized.


Synthesizing Unit <lcd>.
    Related source file is "E:/DEMO_FPGA/lcd_driver.vhd".
INFO:Xst:1799 - State write_data3 is never reached in FSM <current_state>.
INFO:Xst:1799 - State set_location2 is never reached in FSM <current_state>.
INFO:Xst:1799 - State set_cgram_location is never reached in FSM <current_state>.
INFO:Xst:1799 - State write_cgram is never reached in FSM <current_state>.
    Found finite state machine <FSM_1> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 10                                             |
    | Inputs             | 2                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (falling_edge)                             |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | set_dlnf                                       |
    | Power Up State     | set_dlnf                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <lcdda>.
    Found 5-bit register for signal <lcd_address>.
    Found 8-bit register for signal <data>.
    Found 5-bit adder for signal <$n0013> created at line 63.
    Found 5-bit register for signal <cnt2>.
    Summary:
	inferred   1 Finite State Machine(s).