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Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 1 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: 7.329ns Maximum output required time after clock: 6.514ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/DEMO_FPGA/electronic_organ.vhd" in Library work.Entity <electronic_organ> compiled.Entity <electronic_organ> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <electronic_organ> (Architecture <behavioral>).INFO:Xst:1304 - Contents of register <cnt> in unit <electronic_organ> never changes during circuit operation. The register is replaced by logic.Entity <electronic_organ> analyzed. Unit <electronic_organ> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <electronic_organ>. Related source file is "E:/DEMO_FPGA/electronic_organ.vhd". Found 1-bit register for signal <tone>. Found 18-bit comparator greater for signal <$n0003> created at line 53. Found 18-bit comparator greater for signal <$n0010> created at line 53. Summary: inferred 1 D-type flip-flop(s). inferred 2 Comparator(s).Unit <electronic_organ> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 1-bit register : 1# Comparators : 2 18-bit comparator greater : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <electronic_organ> ...Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block electronic_organ, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s100epq208-6 Number of Slices: 6 out of 1200 0% Number of Slice Flip Flops: 1 out of 2400 0% Number of 4 input LUTs: 10 out of 2400 0% Number of bonded IOBs: 6 out of 146 4% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 1 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: 7.329ns Maximum output required time after clock: 6.514ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/DEMO_FPGA/DEMO_ADC.vhd" in Library work.Architecture adc of Entity digital_voltmeter is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <digital_voltmeter> (Architecture <adc>).WARNING:Xst:819 - "E:/DEMO_FPGA/DEMO_ADC.vhd" line 186: The following signals are missing in the process sensitivity list: reg_datain.INFO:Xst:1304 - Contents of register <cs_tlc549> in unit <digital_voltmeter> never changes during circuit operation. The register is replaced by logic.Entity <digital_voltmeter> analyzed. Unit <digital_voltmeter> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <digital_voltmeter>. Related source file is "E:/DEMO_FPGA/DEMO_ADC.vhd". Found finite state machine <FSM_0> for signal <current_state1>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 4 | | Outputs | 3 | | Clock | clk100 (rising_edge) | | Power Up State | st0 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_1> for signal <current_state2>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 5 | | Inputs | 0 | | Outputs | 5 | | Clock | clk1k (rising_edge) | | Power Up State | st0 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <clk_tlc549>. Found 4-bit register for signal <shift>. Found 2-bit register for signal <cs_led>. Found 17-bit comparator greater for signal <$n0012> created at line 134. Found 17-bit comparator greater for signal <$n0013> created at line 134. Found 17-bit comparator greater for signal <$n0014> created at line 135. Found 17-bit comparator greater for signal <$n0015> created at line 136. Found 10-bit comparator less for signal <$n0024> created at line 73. Found 6-bit comparator less for signal <$n0026> created at line 60. Found 4-bit comparator less for signal <$n0040> created at line 86. Found 8x8-bit multiplier for signal <$n0043> created at line 113. Found 10-bit adder for signal <$n0044> created at line 72. Found 6-bit adder for signal <$n0045> created at line 59. Found 4-bit adder for signal <$n0046> created at line 85. Found 17-bit subtractor for signal <$n0047> created at line 134. Found 4-bit adder for signal <$n0049> created at line 134. Found 4-bit adder for signal <$n0050> created at line 135. Found 4-bit adder for signal <$n0051> created at line 136. Found 4-bit adder for signal <$n0052> created at line 137. Found 10-bit comparator less for signal <$n0053> created at line 74. Found 6-bit comparator less for signal <$n0054> created at line 61. Found 4-bit comparator less for signal <$n0055> created at line 87. Found 3-bit comparator less for signal <$n0066> created at line 111. Found 1-bit register for signal <clk100>. Found 1-bit register for signal <clk1k>. Found 1-bit register for signal <clk1m>. Found 6-bit up counter for signal <cnt>. Found 10-bit up counter for signal <cnt0>. Found 4-bit up counter for signal <cnt1>. Found 3-bit up counter for signal <cnt2>. Found 1-bit register for signal <current_state<0>>. Found 4-bit register for signal <d1>. Found 4-bit register for signal <d2>. Found 4-bit register for signal <d3>. Found 4-bit register for signal <d4>. Found 8-bit register for signal <datain>. Found 5-bit register for signal <dout>. Found 17-bit register for signal <reg>. Found 8-bit register for signal <reg_datain>. Found 16-bit register for signal <reg_din>. Found 16-bit register for signal <reg_dout>. Summary: inferred 2 Finite State Machine(s). inferred 4 Counter(s). inferred 97 D-type flip-flop(s). inferred 8 Adder/Subtractor(s). inferred 1 Multiplier(s). inferred 11 Comparator(s).Unit <digital_voltmeter> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.Advanced Registered AddSub inference ...Analyzing FSM <FSM_1> for best encoding.Optimizing FSM <FSM_1> on signal <current_state2[1:5]> with speed1 encoding.------------------- State | Encoding------------------- st0 | 10000 st1 | 01000 st2 | 00100 st3 | 00010 st4 | 00001-------------------Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <current_state1[1:2]> with sequential encoding.------------------- State | Encoding------------------- st0 | 00 st1 | 01 st2 | 10-------------------Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 2# Multipliers : 1 8x8-bit multiplier : 1# Adders/Subtractors : 8 10-bit adder : 1 17-bit subtractor : 1 4-bit adder : 5 6-bit adder : 1# Counters : 4 10-bit up counter : 1 3-bit up counter : 1 4-bit up counter : 1 6-bit up counter : 1# Registers : 31 1-bit register : 20 16-bit register : 2 17-bit register : 1 2-bit register : 1 4-bit register : 5 5-bit register : 1 8-bit register : 1# Comparators : 11 10-bit comparator less : 2 17-bit comparator greater : 4 3-bit comparator less : 1 4-bit comparator less : 2 6-bit comparator less : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Register <current_state_0> equivalent to <clk_tlc549> has been removedWARNING:Xst:1291 - FF/Latch <reg_din_0> is unconnected in block <digital_voltmeter>.WARNING:Xst:1291 - FF/Latch <reg_0> is unconnected in block <digital_voltmeter>.Optimizing unit <digital_voltmeter> ...Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block digital_voltmeter, actual ratio is 14.FlipFlop clk_tlc549 has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s100epq208-6 Number of Slices: 153 out of 1200 12% Number of Slice Flip Flops: 125 out of 2400 5% Number of 4 input LUTs: 249 out of 2400 10% Number of bonded IOBs: 18 out of 146 12% Number of GCLKs: 3 out of 4 75% =========================================================================TIMING REPORT⌨️ 快捷键说明
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